公开(公告)号：US20120299174A1

公开(公告)日：2012-11-29

申请号：US13566872

申请日：2012-08-03

Applicant: DaeSik Choi ,  WonJun Ko ,  JaEun Yun

Inventor： DaeSik Choi ,  WonJun Ko ,  JaEun Yun

IPC: H01L23/52 ,  H01L23/34

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/02371 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/221 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/14364 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.

Abstract translation: 半导体晶片包含多个第一半导体管芯。 半导体晶片安装在载体上。 通过半导体晶片形成通道以分离第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 密封剂沉积在载体和第一半导体管芯上并进入沟道，同时第二半导体管芯的侧部和表面部分保持暴露于密封剂。 通过通道中的密封剂形成第一导电通孔。 第二导电通孔在第一半导体管芯的接触焊盘上穿过密封剂形成。 在第一和第二导电通孔之间的密封剂之上形成导电层。 在导电层和密封剂之上形成绝缘层。 载体被移除。 互连结构形成在第一导电通孔上。

公开(公告)号：US08319932B2

公开(公告)日：2012-11-27

申请号：US12673307

申请日：2008-07-17

Applicant: Takashi Matsui ,  Motoji Shiota

Inventor： Takashi Matsui ,  Motoji Shiota

IPC: G02F1/1345

CPC classification number: H05K1/117 ,  G02F1/1345 ,  G02F1/13458 ,  G02F2001/13629 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/4644 ,  H05K2201/09672 ,  H05K2201/09709 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); each of the first metal wires (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to have a widthwise center in a lower region below the corresponding second-row pad (30b); and each of the first metal wires (10a) has widthwise edges provided, in a plan view, beyond widthwise edges of a corresponding one of the second-row pads (30b) in a region in which the first metal wire (10a) overlaps with the corresponding second-row pad (30b).

Abstract translation: 本发明的布线基板（1）的布置方式为：排列成多行的焊盘（30）包括：与金属线（10）之间的第一金属线（10a）连接的第一排焊盘（30a） 和连接到金属线（10）中的第二金属线（10b）的第二排焊盘（30b），第一金属线（10a）比第二金属线（10b）长; 每个第一金属线（10a）形成为与至少一个绝缘层与相应的第二排焊盘（30b）分离，并且在下面的区域中具有宽度方向的中心 相应的第二排垫（30b）; 并且所述第一金属线（10a）中的每一个具有宽度方向的边缘，所述横向边缘在所述第一金属线（10a）与所述第一金属线（10a）重叠的区域中在所述第二列焊盘（30b）中的相应一个的横向边缘 对应的第二排垫（30b）。

公开(公告)号：US08304277B2

公开(公告)日：2012-11-06

申请号：US12878661

申请日：2010-09-09

Applicant: Reza A. Pagaila

Inventor： Reza A. Pagaila

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/81 ,  H01L2224/45099 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.

Abstract translation: 半导体器件具有基底衬底，其具有形成在基底衬底的相对表面上的第一和第二耐蚀刻导电层。 第一腔通过第一导电层中的开口蚀刻在基底基底中。 第一空腔的宽度大于第一导电层中的开口的宽度。 第二空腔在第一或第二导电层的部分之间在基底衬底中蚀刻。 半导体管芯安装在基底衬底上，凸起设置在第一导电层上。 凸块被回流以电连接到第一导电层并且引起凸块材料流入第一腔。 密封剂沉积在管芯和基底衬底上。 基底衬底的一部分被去除到第二腔，以在第一和第二导电层之间形成电隔离的底部引线。

公开(公告)号：US20120267731A1

公开(公告)日：2012-10-25

申请号：US13498371

申请日：2009-11-18

Applicant: Markus Graf ,  Werner Hunziker ,  Franziska Brem ,  Felix Mayer

Inventor： Markus Graf ,  Werner Hunziker ,  Franziska Brem ,  Felix Mayer

IPC: H01L29/84 ,  H01L21/02

CPC classification number: H01L21/563 ,  G01L19/148 ,  G01N27/128 ,  H01L24/32 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/32225 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2) and located in a chamber (17) between the substrate (1) and the sensor chip (2). Chamber (17) is bordered along at least two sides by a dam (16). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1), and the dam (16) prevents the underfill from entering the chamber (17). An opening (19) extends from the chamber to the environment and is located between the substrate (1) and the sensor chip (2) or extends through the sensor chip (2).

Abstract translation: 该传感器组件包括一个衬底（1），例如柔性印刷电路板，以及安装在衬底（1）上的传感器芯片（2）倒装芯片，其中传感器芯片（2）的第一侧（3） 面向基板（1）。 感测区域（4）和接触焊盘（5）集成在传感器芯片（2）的第一侧（3）上并且位于基板（1）和传感器芯片（2）之间的腔室（17）中。 大厅（17）至少由两座大坝毗邻（16）。 在传感器芯片（2）和基板（1）之间布置有底部填充物（18）和/或焊剂，并且防止底板（16）进入腔室（17）。 开口（19）从腔室延伸到环境并且位于衬底（1）和传感器芯片（2）之间或延伸穿过传感器芯片（2）。

公开(公告)号：US20120264258A1

公开(公告)日：2012-10-18

申请号：US13442878

申请日：2012-04-10

Applicant: Junhua LUO ,  Jinzhong Yao ,  Baoguan Yin

Inventor： Junhua LUO ,  Jinzhong Yao ,  Baoguan Yin

IPC: H01L21/78

CPC classification number: H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.

Abstract translation: 半导体管芯安装在散热片阵列框架结构上。 散热器阵列框架结构和半导体管芯与绝缘基板组装在一起，绝缘基板在胶带上具有相应的孔阵列。 半导体管芯与绝缘基板上的电触点电连接。 半导体管芯，散热器和与触点的电气连接用模具化合物封装，然后封装的阵列被去磁和分离。

公开(公告)号：US20120262231A1

公开(公告)日：2012-10-18

申请号：US13479957

申请日：2012-05-24

Applicant: Mauro SCANDIUZZO ,  Luca Perilli ,  Roberto CANEGALLO

Inventor： Mauro SCANDIUZZO ,  Luca Perilli ,  Roberto CANEGALLO

IPC: H03F3/45 ,  H05K7/06

CPC classification number: H01L23/48 ,  G01R31/3025 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0259 ,  H05K2201/0191 ,  H05K2201/099 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Contactless differential coupling structures can be used to communicate signals between circuits located on separate chips or from one chip to a probing device. The contactless coupling structures avoid problems (breaks, erosion, corrosion) that can degrade the performance of ohmic-type contact pads. The contactless coupling structures comprise pairs of conductive pads placed in close proximity. Differential signals are applied across a first pair of differential pads, and the signals are coupled wirelessly to a mating pair of conductive pads. Circuitry for generating and receiving differential signals is described.

Abstract translation: 非接触式差分耦合结构可以用于在位于单独芯片上或从一个芯片到探测装置的电路之间传送信号。 非接触式耦合结构避免了可能降低欧姆型接触焊盘性能的问题（断裂，侵蚀，腐蚀）。 非接触耦合结构包括靠近放置的一对导电焊盘。 差分信号跨越第一对差分焊盘施加，并且信号被无线地耦合到一对导电焊盘。 描述用于产生和接收差分信号的电路。

公开(公告)号：US20120261171A1

公开(公告)日：2012-10-18

申请号：US13534667

申请日：2012-06-27

Applicant: Yasunobu YAMADA ,  Koichi Miyauchi

Inventor： Yasunobu YAMADA ,  Koichi Miyauchi

IPC: H05K1/18 ,  H05K1/03

CPC classification number: C08L71/00 ,  C08G2650/56 ,  C08K3/08 ,  C08K9/02 ,  C08K2003/0862 ,  C08L33/06 ,  C09J5/06 ,  C09J7/10 ,  C09J9/02 ,  C09J11/02 ,  C09J2201/36 ,  C09J2203/326 ,  C09J2205/102 ,  C09J2433/00 ,  C09J2461/00 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/83201 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/0665 ,  H01L2924/00

Abstract: To provide an anisotropic conductive film, which contains: an electric conductive layer containing Ni particles, metal-coated resin particles, a binder, a polymerizable monomer, and a curing agent; and an insulating layer containing a binder, a monofunctional polymerizable monomer, and a curing agent, wherein the metal-coated resin particles are resin particles each containing a resin core coated at least with Ni.

Abstract translation: 提供各向异性导电膜，其包含：含有Ni颗粒的导电层，金属包覆的树脂颗粒，粘合剂，可聚合单体和固化剂; 以及含有粘合剂，单官能聚合性单体和固化剂的绝缘层，其中，所述金属被覆树脂粒子是各自含有至少涂覆有Ni的树脂核心的树脂粒子。

公开(公告)号：US20120256312A1

公开(公告)日：2012-10-11

申请号：US13525734

申请日：2012-06-18

Applicant: Shinya TSUJIMOTO

Inventor： Shinya TSUJIMOTO

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03474 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81002 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/05155 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip, an electrode pad formed on the semiconductor chip, an underlying barrier metal formed on the electrode pad, a solder bump formed on the underlying barrier metal, and an underfill material surrounding the underlying barrier metal and the solder bump. A junction interface of the solder bump with the underlying barrier metal corresponds to an upper surface of the underlying barrier metal, and a portion of the underfill material bonded to a side surface of the solder bump and an end surface of the underlying barrier metal forms a right angle or an obtuse angle.

Abstract translation: 半导体器件包括半导体芯片，形成在半导体芯片上的电极焊盘，形成在电极焊盘上的下面的阻挡金属，形成在下面的阻挡金属上的焊料凸块，以及围绕下面的阻挡金属和焊料凸块的底部填充材料 。 焊料凸块与下面的阻挡金属的接合界面对应于下面的阻挡金属的上表面，并且底部填充材料的结合到焊料凸块的侧表面的一部分和下面的阻挡金属的端面形成一个 直角或钝角。

公开(公告)号：US20120248539A1

公开(公告)日：2012-10-04

申请号：US13244256

申请日：2011-09-23

Applicant: Xiaotian Zhang ,  Hamza Yilmaz ,  Jun Lu ,  Xiaoguang Zeng ,  Ming-Chen Lu

Inventor： Xiaotian Zhang ,  Hamza Yilmaz ,  Jun Lu ,  Xiaoguang Zeng ,  Ming-Chen Lu

IPC: H01L23/495 ,  H01L27/088

CPC classification number: H01L23/49524 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/84 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40135 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.

Abstract translation: 一种半导体器件封装，包括具有包括第一芯片安装区域和第二芯片安装区域的模板的引线框架，形成在第一芯片安装区域中的凹部区域和形成在凹部区域中的多个金属柱，凹口将 第一芯片安装区域横向延伸的横向基部和纵向延伸的纵向基部，并且将凹部区域分离成形成在横向基部中的横向凹部和形成在纵向基部中的纵向凹部; 连接到外部销的横向延伸部分的一部分延伸到凹口内部的一部分。

公开(公告)号：US08278754B2

公开(公告)日：2012-10-02

申请号：US12582849

申请日：2009-10-21

Applicant: Min-Seok Kim

Inventor： Min-Seok Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76828 ,  H01L24/03 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02125 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03505 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A method includes forming a buffer lower metal line over a semiconductor substrate for absorbing an external impact, forming a pre-metal-dielectric layer which covers the buffer lower metal line, the pre-metal-dielectric layer having a via hole formed therein to expose a portion of the buffer lower metal line, forming a seed layer over a surface of the pre-metal-dielectric layer having the via hole formed therein, forming polyimide which exposes the via hole and the seed layer formed over the pre-metal-dielectric layer in the vicinity of the via hole, growing an upper metal line over the exposed seed layer, subjecting the semiconductor substrate having the upper metal line formed thereon to a thermal process, removing the polyimide by dry etching, and bonding a bonding portion onto the upper metal line.

Abstract translation: 一种方法包括在半导体衬底上形成用于吸收外部冲击的缓冲下金属线，形成覆盖缓冲下金属线的预金属介电层，其中形成有通孔的预金属介电层露出 缓冲下部金属线的一部分，在其上形成有通孔的预金属 - 电介质层的表面上形成晶种层，形成聚酰亚胺，其暴露出在金属前电介质上形成的通孔和晶种层 在通孔的附近形成上金属线，在其上形成具有上金属线的半导体衬底进行热处理，通过干蚀刻去除聚酰亚胺，并将接合部分接合到 上金属线。