公开(公告)号：US07528788B2

公开(公告)日：2009-05-05

申请号：US12174960

申请日：2008-07-17

Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

IPC: H01Q3/40

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

公开(公告)号：US20090095519A1

公开(公告)日：2009-04-16

申请号：US11872870

申请日：2007-10-16

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H05K1/00 ,  H05K3/42

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种电气结构和成型方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。

公开(公告)号：US20090079070A1

公开(公告)日：2009-03-26

申请号：US11858749

申请日：2007-09-20

Applicant: Yaojian Lin ,  Xu Sheng Bao

Inventor： Yaojian Lin ,  Xu Sheng Bao

IPC: H01L23/52 ,  H01L21/60

CPC classification number: H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

Abstract: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

Abstract translation: 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 在基板上形成接触垫。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面没有UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。

公开(公告)号：US20090072374A1

公开(公告)日：2009-03-19

申请号：US11856652

申请日：2007-09-17

Applicant: Stephan Dobritz ,  Christoph Polaczyk ,  Roland Irsigler

Inventor： Stephan Dobritz ,  Christoph Polaczyk ,  Roland Irsigler

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H05K3/3436 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/112 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/096 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment of the present invention, an electric device includes: a top surface and a bottom surface; a contact hole extending from the top surface through the device to the bottom surface; a conductive sealing element which seals the contact hole at or near the bottom surface; a conductive connection which is coupled to the conductive sealing element and which extends through the contact hole to the top surface; and solder material which is provided on a bottom surface of the conductive sealing element.

Abstract translation: 根据本发明的一个实施例，电气设备包括：顶表面和底表面; 从所述顶表面穿过所述装置延伸到所述底表面的接触孔; 导电密封元件，其在底表面处或附近密封接触孔; 导电连接，其连接到导电密封元件并且延伸穿过接触孔到达顶表面; 以及设置在导电性密封元件的底面上的焊料。

公开(公告)号：US20090065920A1

公开(公告)日：2009-03-12

申请号：US12219263

申请日：2008-07-18

Applicant: Eun-Chul Ahn ,  Min-Ho O ,  Jong Ho Lee

Inventor： Eun-Chul Ahn ,  Min-Ho O ,  Jong Ho Lee

IPC: H01L23/488 ,  H01L21/58

CPC classification number: H01L23/13 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/185 ,  H05K2201/09509 ,  H05K2201/10515 ,  H05K2201/10719 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/01049

Abstract: A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package.

Abstract translation: 一种器件包括基底，包括封装的芯片的封装，至少部分地嵌入基底衬底中的封装以及封装上的布线部分，并延伸穿过与封装相邻的基底衬底的至少一部分。

公开(公告)号：US20090057827A1

公开(公告)日：2009-03-05

申请号：US12129889

申请日：2008-05-30

Applicant: Takeshi SHIOGA ,  Masataka MIZUKOSHI ,  Kazuaki KURIHARA

Inventor： Takeshi SHIOGA ,  Masataka MIZUKOSHI ,  Kazuaki KURIHARA

IPC: H01G4/228 ,  H01L21/20 ,  H01L29/00

CPC classification number: H05K1/162 ,  H01G9/025 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract translation: 对于用于半导体集成电路元件的电极焊盘，用于信号传输的一些电极焊盘耦合到Ti膜。 用于信号传输的其他电极焊盘通过布线在多层布线中的布线耦合到电极焊盘。 用于电源的电极焊盘耦合到电极焊盘，电极彼此不同的电力线通过布线耦合到电极焊盘。 电极焊盘也耦合到铝箔（阳极）。 用于接地的电极焊盘耦合到接地线通过布线耦合到的电极焊盘。 电极焊盘也耦合到导电聚合物膜（阴极）。

公开(公告)号：US20090019693A1

公开(公告)日：2009-01-22

申请号：US12237955

申请日：2008-09-25

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H05K3/10

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。

公开(公告)号：US20080283288A1

公开(公告)日：2008-11-20

申请号：US12219381

申请日：2008-07-21

Applicant: Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

Inventor： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

IPC: H05K1/11

CPC classification number: H05K3/462 ,  H01R12/523 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0353 ,  Y10T29/49155

Abstract: A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

Abstract translation: 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于糊状凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

公开(公告)号：US07452568B2

公开(公告)日：2008-11-18

申请号：US11049846

申请日：2005-02-04

Applicant: Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

Inventor： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

IPC: B05D3/12 ,  B05D1/42

CPC classification number: H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract translation: 本公开总体上涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，浆料，材料的悬浮液，以充当导电的结构 支撑或电子部件的保护构件。

公开(公告)号：US20080272982A1

公开(公告)日：2008-11-06

申请号：US12174960

申请日：2008-07-17

Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

IPC: H01Q15/24

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。