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    Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP)
    154.
    发明申请
    Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP) 有权
    半导体器件和形成封装的晶片级芯片级封装（EWLCSP）的方法

    公开(公告)号：US20150243575A1

    公开(公告)日：2015-08-27

    申请号：US14627347

    申请日：2015-02-20

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Thomas J. Strothmann ,  Seung Wook Yoon ,  Yaojian Lin

    IPC: H01L23/31 ,  H01L21/56

    CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/73267 ,  H01L2924/18162 ,  H01L2924/3511

    Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.

    Abstract translation: 半导体器件具有半导体管芯和半导体管芯周围的密封剂。 在半导体管芯上形成扇形互连结构，同时留下没有互连结构的密封剂。 扇形互连结构包括绝缘层和形成在半导体管芯上的导电层。 导电层保持在半导体管芯的覆盖区内。 从半导体管芯上去除一部分密封剂。 在沉积密封剂之后，在半导体管芯的非活性表面上形成背面保护层。 背面保护层通过丝网印刷或层压形成。 背面保护层包括不透明，透明或半透明的材料。 背面保护层被标记为使用激光进行对准。 通过密封剂将包括半导体裸片的复原面板分离，以留下设置在半导体管芯的侧壁上的密封剂。

    Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package
    156.
    发明申请
    Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package 有权
    半导体器件和在扇出封装中形成精细间距RDL超半导体管芯的方法

    公开(公告)号：US20150179570A1

    公开(公告)日：2015-06-25

    申请号：US14139614

    申请日：2013-12-23

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Pandi C. Marimuthu ,  Yaojian Lin ,  Won Kyoung Choi ,  Il Kwon Shim

    IPC: H01L23/522 ,  H01L25/065 ,  H01L21/56

    CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

    Abstract translation: 半导体器件具有包括多个导电迹线的第一导电层。 第一导电层形成在衬底上。 导电迹线以窄间距形成。 第一半导体管芯和第二半导体管芯设置在第一导电层上。 第一密封剂沉积在第一和第二半导体管芯上。 去除衬底。 第二密封剂沉积在第一密封剂上。 在第一导电层和第二密封剂上形成积层互连结构。 积层互连结构包括第二导电层。 第一无源器件设置在第一密封剂中。 第二无源器件设置在第二密封剂中。 垂直互连单元设置在第二密封剂中。 第三导电层形成在第二密封剂之上并且经由垂直互连单元电连接到积层互连结构。

    Semiconductor Device and Method of Wafer Thinning Involving Edge Trimming and CMP
    157.
    发明申请
    Semiconductor Device and Method of Wafer Thinning Involving Edge Trimming and CMP 有权
    半导体器件和涉及边缘修整和CMP的晶片薄化的方法

    公开(公告)号：US20150179544A1

    公开(公告)日：2015-06-25

    申请号：US14134907

    申请日：2013-12-19

    Applicant: STATS CHIPPAC, LTD.

    Inventor： Vinoth Kanna Chockanathan ,  Xing Zhao ,  Duk Ju Na ,  Chang Bum Yong

    IPC: H01L23/48 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/56 ,  H01L21/306

    CPC classification number: H01L21/30625 ,  H01L21/304 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

    Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.

    Abstract translation: 半导体器件具有包括垂直且部分穿过衬底形成的多个导电通孔的衬底。 密封剂沉积在衬底的第一表面上并且围绕衬底的周边区域。 通过切割或激光操作去除围绕周边区域的密封剂的一部分，以形成横向延伸通过密封剂的凹口到衬底的与衬底的第一表面相对的第二表面。 通过化学机械抛光去除凹口外部的基板的第一部分以暴露导电通孔。 在形成凹口之前或之后，通过背面研磨去除衬底的第二部分。 透明导电孔之后，密封剂与基板共面。 密封剂/基材界面的不存在和模塑基材的共面性导致较少的过蚀刻或欠蚀刻和较少的缺陷。

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