公开(公告)号：US20140319702A1

公开(公告)日：2014-10-30

申请号：US14328348

申请日：2014-07-10

Applicant: STATS ChipPAC, Ltd.

Inventor： JoungIn Yang ,  ChoongBin Yim ,  KeonTeak Kang ,  YoungChul Kim

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/28 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/85205 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/83205

Abstract: A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.

Abstract translation: 半导体封装包括衬底，安装到衬底的第一半导体管芯和通过第一粘合剂直接结合到第一半导体管芯的第一双面模具（DSM）内部可堆叠模块（ISM）。 第一DSM ISM包括第一模塑料和设置在第一模塑料中的第二半导体模。 半导体封装还包括耦合在第一半导体管芯和衬底之间的第一电连接以及耦合在第一DSM ISM和衬底之间的第二电连接。

公开(公告)号：US20140319692A1

公开(公告)日：2014-10-30

申请号：US14329162

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0901 ,  H01L2224/1134 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.

Abstract translation: 半导体器件具有在半导体管芯的表面上的接触焊盘上形成有多个凸点的半导体管芯。 凸块可以具有可熔部分和非易熔部分。 在衬底上形成多个导电迹线，其互连位置的宽度大于凸块和接触焊盘之间的接触界面的20％且小于80％的宽度。 这些凸块被结合到互连部位，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。 导电迹线具有通过可以放置在衬底上的相邻导电迹线之间的最小间隔确定的间距，并且互连部位的宽度提供等于导电迹线的间距的布线密度。

公开(公告)号：US20140300002A1

公开(公告)日：2014-10-09

申请号：US14222547

申请日：2014-03-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Chang Beom Yong ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

Abstract translation: 半导体器件包括多个半导体管芯和形成在半导体管芯中的多个导电通孔。 在半导体管芯上形成绝缘层，同时使导电通孔露出。 在绝缘层和导电通孔上形成互连结构。 绝缘层使用电动或氧化形成。 在导电通孔上形成凸块下金属化。 去除半导体管芯的一部分以露出导电通孔。 互连结构形成在两个或更多个导电通孔上。 去除半导体管芯的一部分以留下具有大于半导体管芯高度的高度的导电通孔。 在第一绝缘层上形成第二绝缘层。 去除第二绝缘层的一部分以露出导电通孔。

公开(公告)号：US20140269810A1

公开(公告)日：2014-09-18

申请号：US13846593

申请日：2013-03-18

Applicant: STATS CHIPPAC, LTD.

Inventor： WonJun Ko ,  SeungYong Chai ,  OhHan Kim ,  GwangTae Kim ,  Kenny Lee

IPC: G01N25/72

CPC classification number: G01B11/306 ,  H01L22/12

Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Abstract translation: 翘曲测试系统使用校准块在温度曲线上校准翘曲测试系统。 校准块包括结合到第二金属块的第一金属块。 第一金属块包括第一金属和第二不同的金属。 第一金属块包括与第二金属块的CTE不同的CTE。 校准块设置在翘曲测试系统中。 在28℃至260℃的温度曲线上测量校准块的翘曲。记录校准块的测量翘曲与校准块在温度曲线上的已知热膨胀之间的偏差。 半导体封装中的翘曲测量通过校准块的测量翘曲与校准块在温度曲线上的已知热膨胀或翘曲之间的偏差来补偿。

公开(公告)号：US20140264905A1

公开(公告)日：2014-09-18

申请号：US13801294

申请日：2013-03-13

Applicant: STATS CHIPPAC, LTD.

Inventor： KyungHoon Lee ,  HyunJin Song ,  KyoungIl Huh ,  DaeSik Choi

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 在密封剂和半导体管芯的第一表面之上形成绝缘层。 半导体元件设置在半导体管芯的绝缘层和第一表面之上。 第一互连结构形成在半导体管芯的密封剂和第一表面上以嵌入半导体部件。 在半导体管芯中形成导电通孔。 在半导体管芯上形成散热器。 第二互连结构形成在与第一表面相对的半导体管芯的第二表面上。 在半导体部件上形成导电层。 在绝缘层中形成开口。

公开(公告)号：US08823182B2

公开(公告)日：2014-09-02

申请号：US13935963

申请日：2013-07-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/552 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/17 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L29/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Abstract translation: 半导体器件具有在载体上形成的导电柱。 第一半导体管芯安装在载体之间的导电柱之间。 密封剂沉积在第一半导体管芯和载体上并且围绕导电柱。 在第一半导体管芯上的密封剂的第一表面中形成凹部。 凹槽有倾斜或阶梯。 在密封剂的第一表面上形成第一互连结构。 第一互连结构遵循密封剂中的凹部的轮廓。 载体被移除。 在密封剂和第一半导体管芯的第二表面上形成第二互连结构。 第一和第二互连结构电连接到导电柱。 第二半导体管芯安装在凹槽中。 第三半导体管芯安装在凹槽和第二半导体管芯上。

公开(公告)号：US20140231989A1

公开(公告)日：2014-08-21

申请号：US14265782

申请日：2014-04-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  JunMo Koo

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3677 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.

Abstract translation: 半导体器件具有形成在第一半导体管芯的表面上的多个凸点的半导体管芯。 在临时载体上形成可穿透的粘合剂层。 粘合剂层可以包括多个槽。 通过将凸块嵌入到可穿透的粘合剂层中，将半导体管芯安装到载体上。 半导体管芯和互连结构可以通过间隙分开。 密封剂沉积在第一半导体管芯上。 嵌入可渗透粘合剂层中的凸起减少了第一半导体管芯的移动，同时沉积密封剂。 载体被移除。 在半导体管芯上形成互连结构。 互连结构电连接到凸块。 导热凸块形成在半导体管芯上，并且散热器安装到互连结构并热连接到导热凸块。

公开(公告)号：US20140225256A1

公开(公告)日：2014-08-14

申请号：US14256047

申请日：2014-04-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Jen Yu Chen ,  Ting Yu Fu ,  Men Hsien Li ,  Chien Chen Lee

IPC: H01L23/00

CPC classification number: H01L24/10 ,  H01L22/12 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16058 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection.

Abstract translation: 半导体器件具有在半导体管芯的表面上形成的具有凹部或突起的半导体管芯和导电柱。 导电柱通过在半导体管芯上形成图案化层而形成，在图案化层中形成具有凹部或突起的开口，在开口和凹部或突起中沉积导电材料，并除去图案形成层。 衬底具有沉积在形成在衬底的表面上的导电层上的凸起材料。 凸块材料熔化。 如果导电柱与导电层连接，则将半导体管芯压向衬底，以使熔融的凸块材料流入凹槽或突出部上。 通过X射线或视觉检查来检测导电柱的凹部或突起中是否存在凸块材料。

公开(公告)号：US20140175642A1

公开(公告)日：2014-06-26

申请号：US14192706

申请日：2014-02-27

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有在半导体管芯的表面上形成的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US08759155B2

公开(公告)日：2014-06-24

申请号：US13782618

申请日：2013-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L27/08

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。