公开(公告)号：US09799582B2

公开(公告)日：2017-10-24

申请号：US15488972

申请日：2017-04-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen

IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L23/3192 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13541 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/206 ,  H01L2224/05552

摘要： Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.

公开(公告)号：US09793229B1

公开(公告)日：2017-10-17

申请号：US15455138

申请日：2017-03-10

申请人： ChipMOS Technologies Inc.

发明人： En-Sung Hu

IPC分类号： H01L23/12 ,  H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/4846 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/02206 ,  H01L2224/02317 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05027 ,  H01L2224/4805

摘要： A re-distribution layer structure is adapted to be disposed on a substrate having a pad and a protective layer which has a first opening exposing a part of the pad. The re-distribution layer structure includes a first and a second patterned insulating layers and a re-distribution layer. The first patterned insulating layer is disposed on the protective layer and includes at least one protrusion and a second opening corresponding to the first opening. The re-distribution layer is disposed on the first patterned insulating layer and includes a pad portion and a wire portion. The pad portion is located on the first patterned insulating layer. The wire portion includes a body and at least one trench caved in the body. The body extends from the pad portion to the pad exposed by the first and the second openings. The body covers the protrusion, and the at least one protrusion extends into the at least one trench. The second patterned insulating layer covers the wire portion and exposes a part of the pad portion. A manufacturing method of re-distribution layer structure is further provided.

公开(公告)号：US09761555B2

公开(公告)日：2017-09-12

申请号：US14604525

申请日：2015-01-23

申请人： XINTEC INC.

发明人： Jiun-Yen Lai ,  Yu-Wen Hu ,  Bai-Yao Lou ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Hsin Kuan

IPC分类号： H01L31/00 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L24/81 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03902 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

摘要： A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

公开(公告)号：US20170229413A1

公开(公告)日：2017-08-10

申请号：US15498659

申请日：2017-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13541 ,  H01L2224/1405 ,  H01L2224/141 ,  H01L2224/16105 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

摘要： A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

公开(公告)号：US09716034B2

公开(公告)日：2017-07-25

申请号：US14918316

申请日：2015-10-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L21/285 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC分类号： H01L21/76849 ,  H01L21/02271 ,  H01L21/28008 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1015 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/13091

摘要： A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

公开(公告)号：US20170170161A1

公开(公告)日：2017-06-15

申请号：US15443827

申请日：2017-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Hsien-Wen Liu ,  Min-Chen Lin

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11013 ,  H01L2224/1134 ,  H01L2224/1148 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014

摘要： An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

公开(公告)号：US20170133335A1

公开(公告)日：2017-05-11

申请号：US15336774

申请日：2016-10-27

申请人： NXP B.V.

发明人： Chi Ho Leung ,  Pompeo V. Umali ,  Shun Tik Yeung ,  Wai (Kan Wae) Lam

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/03013 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/013

摘要： A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

公开(公告)号：US09613914B2

公开(公告)日：2017-04-04

申请号：US13313811

申请日：2011-12-07

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/525

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/00

摘要： A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

公开(公告)号：US09576923B2

公开(公告)日：2017-02-21

申请号：US14242008

申请日：2014-04-01

申请人： Roden R. Topacio ,  Suming Hu ,  Yip Seng Low

发明人： Roden R. Topacio ,  Suming Hu ,  Yip Seng Low

IPC分类号： H01L23/00 ,  H05K3/34 ,  H05K3/46

CPC分类号： H01L24/16 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/03831 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/05681 ,  H01L2224/085 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/16057 ,  H01L2224/16104 ,  H01L2224/16221 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K3/4629 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

摘要： Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.

摘要翻译： 公开了各种半导体芯片焊料凸块和底部金属化（UBM）结构及其制造方法。 一方面，提供了一种方法，其包括在半导体芯片上形成第一底部金属化层。 第一底部浸渍金属化层具有毂，从轮毂横向延伸的第一部分和将轮毂连接到第一部分的辐条。 将聚合物层施加到第一底部金属化层。 聚合物层包括与轮毂对准的第一开口和与轮辐对准的第二开口。 轮辐的一部分经由第二开口移除以切断轮毂与第一部分之间的连接。

公开(公告)号：US20170005052A1

公开(公告)日：2017-01-05

申请号：US14788182

申请日：2015-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yu Chen ,  Hsien-Wei Chen ,  An-Jhih Su ,  Cheng-Hsien Hsieh

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L21/76885 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/02245 ,  H01L2224/02251 ,  H01L2224/02255 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03472 ,  H01L2224/03622 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05575 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/73267 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.

摘要翻译： 器件封装包括管芯上的管芯，扇出的再分布层（RDL）以及在扇出RDL上的凸起下冶金（UBM）。 UBM包括导电焊盘部分和环绕导电焊盘部分的沟槽。 器件封装还包括设置在UBM的导电焊盘部分上的连接器。 扇出式RDL将连接器和UBM电连接到管芯。