公开(公告)号：US09385101B2

公开(公告)日：2016-07-05

申请号：US14745056

申请日：2015-06-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L33/62

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/27013 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13109 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

公开(公告)号：US09385074B2

公开(公告)日：2016-07-05

申请号：US13935053

申请日：2013-07-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/435 ,  H01L2224/45144 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Abstract translation: 一种半导体封装，其具有嵌入裸片和固体垂直互连（例如柱形凸块互连），用于在z轴方向（即，垂直于模具的电路侧的方向）上增加集成。 半导体封装可以包括以面朝上配置（类似于引线键合封装）或面朝下或倒装芯片配置安装的管芯。

公开(公告)号：US09385052B2

公开(公告)日：2016-07-05

申请号：US13832118

申请日：2013-03-15

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/66 ,  H01L21/56 ,  H01L23/498 ,  H01L23/28 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract translation: 半导体器件具有形成在载体上的第一互连结构。 在测试第一互连结构之后，将半导体管芯设置在第一互连结构上以使其已知良好。 半导体芯片在一个已知的好的芯片中。 在第一互连结构上形成垂直互连结构，例如凸块或凸块凸块。 分立半导体器件设置在第一互连结构或第二互连结构上。 密封剂沉积在半导体管芯，第一互连结构和垂直互连结构之上。 去除一部分密封剂以露出垂直互连结构。 第二互连结构形成在密封剂上并电连接到垂直互连结构。 第一互连结构或第二互连结构包括具有嵌入的玻璃布，玻璃交叉，填充物或纤维的绝缘层。

公开(公告)号：US09337141B2

公开(公告)日：2016-05-10

申请号：US13622280

申请日：2012-09-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/20 ,  H01L23/522 ,  H01L23/64 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract translation: 半导体器件具有在其表面上形成有电感器的基板。 第一和第二接触垫形成在基板上。 在衬底和第一和第二接触焊盘之上形成钝化层。 在钝化层上形成保护层。 保护层在第一接触垫上移除，但不从第二接触垫移除。 导电层形成在第一接触焊盘上。 导电层被卷绕在基板的表面上以产生电感性质。 导电层的形成涉及使用湿蚀刻剂。 第二接触垫被保护层从湿蚀刻剂保护。 在第一接触垫上形成导电层之后，从第二接触焊盘去除保护层。 在第二接触垫上形成外部连接。

公开(公告)号：US20160118333A1

公开(公告)日：2016-04-28

申请号：US14971627

申请日：2015-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L25/00 ,  H01L23/31 ,  H01L25/16 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L23/528 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/03334 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供第一生产线，提供第二生产线，以及使用第一生产线形成第一再分配互连结构，同时使用第二生产线形成第二再分布互连结构。 该方法还包括以下步骤：测试第一再分布互连结构的第一单元以确定第一已知良好单元（KGU），在第一再分配互连结构的第一KGU上设置已知的良好半导体管芯（KGD），以及切割 第一个再分配互连结构的KGU和KGD。 该方法还包括以下步骤：测试第二再分配互连结构的单元以确定第二再分布互连结构的第二KGU，并且将第一再分布互连结构的第一KGU和KGD布置在第二再分配互连结构的第二KGU上 。

公开(公告)号：US20160111410A1

公开(公告)日：2016-04-21

申请号：US14971291

申请日：2015-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

公开(公告)号：US09263332B2

公开(公告)日：2016-02-16

申请号：US13943737

申请日：2013-07-16

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC: H01L23/02 ,  H01L21/78 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/11003 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.

公开(公告)号：US20150348936A1

公开(公告)日：2015-12-03

申请号：US14721677

申请日：2015-05-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

Abstract translation: 半导体器件具有第一部件。 模块化互连结构被布置成与第一部件相邻。 在第一组件和模块化互连结构上形成第一互连结构。 在第一组件，模块化互连结构和第一互连结构上形成屏蔽层。 屏蔽层为封闭的半导体器件提供防止EMI，RFI或其他器件间干扰的保护，无论是内部产生还是从外部半导体器件产生。 屏蔽层电连接到外部低阻抗接地点。 第二部件邻近第一部件设置。 第二组件包括无源设备。 LC电路包括第一部件和第二部件。 将半导体管芯设置成与第一部件相邻。 导电粘合剂设置在模块化互连结构之上。 模块化互连结构包括小于第一部件的高度的高度。

公开(公告)号：US09184139B2

公开(公告)日：2015-11-10

申请号：US14109313

申请日：2013-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate including a base substrate material and a plurality of conductive vias formed partially though the substrate. A plurality of semiconductor die including a base semiconductor material is disposed over the substrate. A ratio of an encapsulant to a quantity of the semiconductor die is determined for providing structural support for the semiconductor die. An encapsulant is deposited over the semiconductor die and substrate. An amount of the encapsulant is selected based on the determined ratio or based on a total amount of the base substrate material and base semiconductor material. Channels are formed in the encapsulant by removing a portion of the encapsulant in a peripheral region of the semiconductor die. Alternatively, a side surface of the semiconductor die is partially exposed with respect to the encapsulant. A portion of the base substrate material is removed to expose the conductive vias.

Abstract translation: 半导体器件具有包括基底材料和部分地通过衬底形成的多个导电通孔的衬底。 包括基底半导体材料的多个半导体管芯设置在基板上。 确定密封剂与半导体管芯的量的比率以提供半导体管芯的结构支撑。 密封剂沉积在半导体管芯和衬底上。 基于确定的比例或基于基底材料和基底半导体材料的总量来选择一定量的密封剂。 通过在半导体管芯的周边区域中去除一部分密封剂而在密封剂中形成通道。 或者，半导体管芯的侧表面相对于密封剂部分地露出。 去除基底衬底材料的一部分以露出导电通孔。

公开(公告)号：US20150279815A1

公开(公告)日：2015-10-01

申请号：US14228769

申请日：2014-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Sung Soo Kim

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01082 ,  H01L2224/81805 ,  H01L2224/45099

Abstract: A semiconductor device has a first conductive layer disposed over a carrier. A second conductive layer is formed over a first surface of the first conductive layer. A first insulating layer is formed over the first and second conductive layers. A third conductive layer is formed over the first insulating layer. A second insulating layer is formed over the third conductive layer. The carrier is removed to expose the first conductive layer. A portion of the first conductive layer is removed from a second surface of the first conductive layer opposite the first surface to form a plurality of conductive pillars. The conductive pillars include a height of 100 micrometers or greater. The portion of the first conductive layer is removed using an etching process. The conductive pillars are disposed over a first semiconductor package. A semiconductor die or second semiconductor package is disposed over the second conductive layer.

Abstract translation: 半导体器件具有设置在载体上的第一导电层。 在第一导电层的第一表面上形成第二导电层。 在第一和第二导电层上形成第一绝缘层。 在第一绝缘层上形成第三导电层。 在第三导电层上形成第二绝缘层。 移除载体以露出第一导电层。 第一导电层的一部分从与第一表面相对的第一导电层的第二表面去除以形成多个导电柱。 导电柱包括100微米或更大的高度。 使用蚀刻工艺去除第一导电层的部分。 导电柱设置在第一半导体封装之上。 半导体管芯或第二半导体封装设置在第二导电层上。