公开(公告)号：US09881854B2

公开(公告)日：2018-01-30

申请号：US15341735

申请日：2016-11-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Phuong Trong Le ,  Alexander Young

IPC: H01L29/15 ,  H01L23/495 ,  H01L29/78 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/7816 ,  H01L29/7817 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically coupled with the base. A depletion mode gallium nitride field-effect transistor (GaN FET) and an enhancement mode laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS FET) are also coupled with the base. The gate connector and a gate contact of the LDMOS FET are both included in a first electrical node, the source connector and a source contact of the LDMOS FET are both included in a second electrical node, and the drain connector and a drain contact of the GaN FET are both included in a third electrical node. The GaN FET and LDMOS FET together form a cascode that operates as an enhancement mode amplifier. The semiconductor package does not include an interposer between the GaN FET and the base or between the LDMOS FET and the base.

公开(公告)号：US09837393B2

公开(公告)日：2017-12-05

申请号：US15349395

申请日：2016-11-11

Applicant: Infineon Technologies Americas Corp.

Inventor： Martin Standing

IPC: H01L25/16 ,  H01L23/49 ,  H01L23/492 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/11 ,  H01L25/065 ,  H01L23/50

CPC classification number: H01L25/16 ,  H01L23/492 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/115 ,  H01L25/162 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1411 ,  H01L2224/16225 ,  H01L2224/29026 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/83851 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

公开(公告)号：US20170338197A1

公开(公告)日：2017-11-23

申请号：US15674406

申请日：2017-08-10

Applicant: Renesas Electronics Corporation

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  G02F1/133 ,  H01L23/528 ,  H01L23/522 ,  H01L23/485 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  G02F1/1345 ,  G02F1/1343 ,  G02F1/1333 ,  H01L27/13 ,  H01L29/78 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US09807916B2

公开(公告)日：2017-10-31

申请号：US14090534

申请日：2013-11-26

Applicant: Taiyo Yuden Co., Ltd.

Inventor： Kenzo Kitazaki ,  Masaya Shimamura ,  Eiji Mugiya ,  Takehiko Kai

IPC: H05K9/00 ,  H01L23/00 ,  H05K3/30 ,  H01L23/31 ,  H01L21/56 ,  H01L23/552 ,  H01L23/29 ,  H01L25/065

CPC classification number: H05K9/0015 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/301 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit module includes a wiring substrate having a mount surface, a conductor pattern, and an insulating protective layer, the mount surface having first and second areas, the conductor pattern being formed along a boundary between the first and second areas on the mount surface, the insulating protective layer being formed on the mount surface, the insulating protective layer covering the mount surface and the conductor pattern; a plurality of electronic components mounted on the first and second areas; an insulating sealing layer having a trench, the insulating sealing layer covering the plurality of electronic components, the trench having a depth such that the trench penetrates the protective layer to reach a surface of the conductive pattern; and a conductive shield having first and second shield portions, the first shield portion covering an outer surface of the sealing layer, the second shield portion being electrically connected to the conductor pattern.

公开(公告)号：US20170294395A1

公开(公告)日：2017-10-12

申请号：US15442263

申请日：2017-02-24

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akihiko HAPPOYA

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/29 ,  H01L23/49513 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0381 ,  H01L2224/03848 ,  H01L2224/04026 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/0569 ,  H01L2224/05693 ,  H01L2224/27436 ,  H01L2224/27438 ,  H01L2224/27848 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a base, a semiconductor chip on the base, a conductive bonding layer between a surface of the base and a surface of the semiconductor chip, the conductive bonding layer including a resin and a plurality of conductive particles contained in the resin, and a molecular bonding layer between the surface of the semiconductor chip and a surface of the conductive bonding layer, and including a molecular portion covalently bonded to a material of the semiconductor chip and a material of the conductive bonding layer.

公开(公告)号：US09779967B2

公开(公告)日：2017-10-03

申请号：US14854140

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Juan A Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32104 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/00

Abstract: A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.

公开(公告)号：US09777197B2

公开(公告)日：2017-10-03

申请号：US14512535

申请日：2014-10-13

Applicant: SunRay Scientific LLC

Inventor： S. Kumar Khanna

IPC: C09J9/02 ,  C09J9/00 ,  H05K13/04 ,  H05K3/30 ,  H05K3/32 ,  H01L23/00 ,  C08K9/02

CPC classification number: C09J9/02 ,  C08K9/02 ,  C08K2201/001 ,  C08K2201/01 ,  C09J9/00 ,  H01L24/29 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29388 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/75253 ,  H01L2224/75265 ,  H01L2224/75266 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/81193 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83874 ,  H01L2224/8393 ,  H01L2924/00014 ,  H05K3/323 ,  H05K2201/0218 ,  H05K2201/0221 ,  H05K2201/0323 ,  H05K2201/083 ,  H05K2203/104 ,  H01L2924/2064 ,  H01L2924/0665 ,  H01L2224/0401

Abstract: Illustrative embodiments of anisotropic conductive adhesive (ACA) and associated methods are disclosed. In one illustrative embodiment, the ACA may comprise a binder curable using UV light and a plurality of particles suspended in the binder. Each of the plurality of particles may comprise a ferromagnetic material coated with a layer of electrically conductive material. The electrically conducting material may form electrically conductive and isolated parallel paths when the ACA is cured using UV light after being subjected to a magnetic field.

公开(公告)号：US20170271300A1

公开(公告)日：2017-09-21

申请号：US15589614

申请日：2017-05-08

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Masataka WATANABE

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/683 ,  H01L29/66 ,  H01L29/737 ,  H01L23/367

CPC classification number: H01L24/83 ,  H01L21/30612 ,  H01L21/6835 ,  H01L23/367 ,  H01L24/27 ,  H01L29/0692 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/2745 ,  H01L2224/83851

Abstract: A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa. The metal layer, which is in contact with the primary mesa, may be made of at least one of tungsten (W), molybdenum (Mo), and tantalum (Ta) with a thickness of the 10 to 60 nm.

公开(公告)号：US09748197B2

公开(公告)日：2017-08-29

申请号：US15192760

申请日：2016-06-24

Applicant: Altera Corporation

Inventor： Loon Kwang Tan ,  Yuanlin Xie ,  Ping Chet Tan

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/36 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/1624 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/83851 ,  H01L2224/85005 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85664 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/364 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

公开(公告)号：US20170221869A1

公开(公告)日：2017-08-03

申请号：US15484499

申请日：2017-04-11

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Jürgen Moosburger ,  Lutz Höppel ,  Norwin von Malm

IPC: H01L25/16 ,  H01L33/56 ,  H01L29/861 ,  H01L33/62 ,  H01L33/54

CPC classification number: H01L25/167 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L29/861 ,  H01L33/54 ,  H01L33/56 ,  H01L33/62 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/03334 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13147 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of producing an optoelectronic component includes providing an optoelectronic semiconductor chip having a first surface on which a first electrical contact and a second electrical contact are arranged; arranging a protection diode on the first contact and the second contact; galvanically growing a first pin on the first electrical contact and a second pin on the second electrical contact; and embedding the first pin, the second pin, and the protection diode in a molded body.