公开(公告)号：US20170033074A1

公开(公告)日：2017-02-02

申请号：US15293549

申请日：2016-10-14

Applicant: Renesas Electronics Corporation

Inventor： Akira YAJIMA

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0519 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/43985 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/4941 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/01047 ,  H01L2924/13091 ,  H01L2924/00014

Abstract: A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A redistribution layer is formed in the polyimide resin film of a single layer. A wiring material (silver) including the redistribution layer can be inhibited from migrating.

Abstract translation: 半导体器件包括在单层的聚酰亚胺树脂膜中整体形成的开口和再分布层沟槽。 在单层的聚酰亚胺树脂膜中形成再分布层。 可以抑制包含再分配层的布线材料（银）的迁移。

公开(公告)号：US09548289B2

公开(公告)日：2017-01-17

申请号：US14741796

申请日：2015-06-17

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ming-Tzong Yang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L25/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/112 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一通孔设置在第一半导体管芯上，耦合到第一焊盘。 第一动态随机存取存储器（DRAM）管芯安装在第一半导体管芯上，耦合到第一通孔。 第二半导体封装堆叠在第一半导体封装上。 第二半导体封装包括具有管芯附接表面和与管芯附接表面相对的凸起附着表面的主体。 第二动态随机存取存储器（DRAM）裸片安装在芯片附接表面上，通过接合线耦合到主体。 第一DRAM裸片的输入/输出（I / O）引脚的数量与第二DRAM裸片的输入/输出（I / O）引脚的数量不同。

公开(公告)号：US20160343615A1

公开(公告)日：2016-11-24

申请号：US15225521

申请日：2016-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC: H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/29 ,  H01L25/065 ,  H01L23/00 ,  H01L21/3105

CPC classification number: H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

公开(公告)号：US09461019B2

公开(公告)日：2016-10-04

申请号：US14948128

申请日：2015-11-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroki Miyajima

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/146 ,  H01L2924/18162 ,  H01L2224/80 ,  H01L2224/84

Abstract: Disclosed herein is a semiconductor device including: a first substrate provided with a first surface layer including a first electrode; an expanded second substrate provided with a second surface layer including a second electrode and directly bonded to the first substrate so that the second surface layer contacts with the first surface layer; and a through electrode running through the first or second substrate. The second surface layer is provided over an expanded second principal surface defined by a second substrate and a resin portion. The second substrate has a smaller planar size than the first substrate. The first and second electrodes are connected together and in contact with each other.

Abstract translation: 本文公开了一种半导体器件，包括：第一衬底，其设置有包括第一电极的第一表面层; 扩展的第二基板，设置有包括第二电极并且直接接合到第一基板的第二表面层，使得第二表面层与第一表面层接触; 以及贯穿第一或第二基板的贯通电极。 第二表面层设置在由第二基板和树脂部分限定的扩展的第二主表面上。 第二基板具有比第一基板更小的平面尺寸。 第一和第二电极彼此连接在一起并且彼此接触。

公开(公告)号：US20160233165A1

公开(公告)日：2016-08-11

申请号：US15131966

申请日：2016-04-18

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba ,  Piyush Savalia

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L27/146 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L29/0657 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract translation: 一种结构，包括具有前表面和后表面的第一半导体芯片以及后表面中的空腔。 第二个半导体芯片安装在腔内。 第一芯片可以具有从空腔延伸到前表面的通孔，以及用于将附加的微电子元件连接到第一芯片的有源元件的这些通孔内的导体。 该结构可以具有与第一芯片单独的体积相当的体积，并且提供多芯片组件的功能。 安装在主体的前表面上的主体和半导体材料层的复合芯片类似地可以具有从后表面延伸到主体中的空腔，并且可以具有安装在该空腔中的附加的微电子元件。

公开(公告)号：US09373597B2

公开(公告)日：2016-06-21

申请号：US14662151

申请日：2015-03-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/00 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L24/14 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/02233 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract translation: 本发明提供了一种芯片封装，其包括半导体芯片，至少一个凹槽，多个第一再分布金属线以及至少一个突起。 半导体芯片具有设置在半导体芯片的上表面上的多个导电焊盘。 凹部从半导体芯片的上表面延伸到下表面，并且布置在半导体芯片的侧面上。 第一再分布金属线设置在上表面上，分别电连接到导电垫，并分别延伸到凹槽中。 突出部设置在凹部中并且位于相邻的第一再分布金属线之间。

公开(公告)号：US09373527B2

公开(公告)日：2016-06-21

申请号：US14147316

申请日：2014-01-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh ,  Kuo-Chung Yee ,  Jui-Pin Hung

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11616 ,  H01L2224/11622 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2924/00012

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Abstract translation: 提供一种用于封装半导体器件的系统和方法。 一个实施例包括在载体晶片上形成通孔并将第一裸片附着在载体晶片上并且在前两个通孔之间。 第二管芯附着在载体晶片上并且在第二个两个通孔之间。 第一管芯和第二管芯被封装以形成第一封装，并且至少一个第三管芯连接到第一管芯或第二管芯。 第二包装通过至少一个第三管芯连接到第一封装。

公开(公告)号：US20150348865A1

公开(公告)日：2015-12-03

申请号：US14291547

申请日：2014-05-30

Applicant: MICHAEL B. VINCENT ,  SCOTT M. HAYES

Inventor： MICHAEL B. VINCENT ,  SCOTT M. HAYES

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/58 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/83 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2731 ,  H01L2224/32175 ,  H01L2224/73267 ,  H01L2224/8384 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/18162 ,  H01L2924/3025

Abstract: Microelectronic packages and methods for producing microelectronic packages having sidewall-deposited heat spreader structures are provided. In one embodiment, the method includes providing a package body containing a microelectronic device. A heat spreader structure is printed or otherwise formed over at least one sidewall of the package body. The heat spreader structure is thermally coupled to the microelectronic device and is configured to dissipate heat generated thereby during operation of the microelectronic package.

Abstract translation: 提供了微电子封装和用于制造具有侧壁沉积的散热器结构的微电子封装的方法。 在一个实施例中，该方法包括提供包含微电子器件的封装主体。 在包装体的至少一个侧壁上印刷或以其它方式形成散热器结构。 散热器结构热耦合到微电子器件，并且被配置为在微电子封装的操作期间散发由此产生的热量。

公开(公告)号：US09190348B2

公开(公告)日：2015-11-17

申请号：US14302117

申请日：2014-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Feng Chen ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Sheng-Yu Wu ,  Chen-Shien Chen

IPC: H01L23/485 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/768 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/485 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13172 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/381 ,  H01L2924/207 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

Abstract translation: 提供一种用于防止钝化层中的裂纹的系统和方法。 在一个实施例中，接触垫具有第一直径，并且穿过钝化层的开口具有第二直径，其中第一直径大于第二直径大约10μm的第一距离。 在另一个实施例中，通过该开口形成底部凹凸金属化，并且下凸块金属化具有大于第一直径的第三直径约5微米的第二距离。 在另一个实施例中，第一距离和第二距离之和大于约15μm。 在另一个实施例中，下凸点金属化具有小于接触焊盘的尺寸的第一尺寸和大于接触焊盘尺寸的第二尺寸。

公开(公告)号：US20150325497A1

公开(公告)日：2015-11-12

申请号：US14657354

申请日：2015-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/48 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/80001 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00014

Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

Abstract translation: 本文公开了具有设置在第一半导体衬底上的第一再分布层（RDL）和设置在第二半导体衬底上的第二RDL的封装。 第一个RDL被绑定到第二个RDL。 封装还包括布置在第二RDL上并围绕第一RDL和第一半导体衬底的绝缘膜。 导电元件设置在第一RDL中。 通孔从绝缘膜的顶表面延伸穿过第一半导体衬底到导电元件，并且间隔物设置在第一半导体衬底和通孔之间。 间隔物延伸穿过第一半导体衬底。