公开(公告)号：US09209140B2

公开(公告)日：2015-12-08

申请号：US14015808

申请日：2013-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Feng Chen ,  Kai-Chiang Wu ,  Chun-Lin Lu ,  Hung-Jui Kuo

IPC分类号： H01L23/58 ,  H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768

CPC分类号： H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA.

摘要翻译： 公开了半导体器件及其制造方法。 在一些实施例中，半导体器件包括衬底以及设置在衬底上的多个接触焊盘。 接触垫布置成球栅阵列（BGA），并且BGA包括多个拐角。 在BGA的多个拐角的每一个周围设置一个金属坝。

公开(公告)号：US20150325482A1

公开(公告)日：2015-11-12

申请号：US14272952

申请日：2014-05-08

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xiang Hu ,  Huang Liu

IPC分类号： H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L21/308

CPC分类号： H01L21/28123 ,  H01L21/28035 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/6681

摘要： Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

摘要翻译： 提供了具有改进的栅极结构的集成电路和用于制造具有改进的栅极结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有鳍结构的半导体衬底。 栅极形成材料沉积在半导体衬底和鳍结构上。 该方法包括执行第一蚀刻工艺以蚀刻栅极形成材料以形成具有第一侧和第二侧的栅极线。 栅极线的第一侧和第二侧与材料有界。 该方法包括执行第二蚀刻工艺以蚀刻由材料限定的栅极线的一部分，以将栅极线分离成相邻的栅极结构并且限定相邻栅极结构之间的尖端到尖端的距离。

公开(公告)号：US20150303157A1

公开(公告)日：2015-10-22

申请号：US14754293

申请日：2015-06-29

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC分类号： H01L23/00 ,  H01L21/3213

CPC分类号： H01L24/11 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/0362 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05578 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05664 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/81815 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00

摘要： An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process.

公开(公告)号：US20150286132A1

公开(公告)日：2015-10-08

申请号：US14743052

申请日：2015-06-18

申请人： HOYA CORPORATION

发明人： Kazuya SAKAI ,  Masahiro HASHIMOTO

IPC分类号： G03F1/50

CPC分类号： G03F1/50 ,  G03F1/46 ,  G03F1/82 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3213 ,  H01L21/32136

摘要： Provided is a method of manufacturing a mask blank that is improved in cleaning resistance to ozone cleaning or the like, thus capable of preventing degradation of the mask performance due to the cleaning. The method is for manufacturing a mask blank having, on a substrate, a thin film which is formed at its surface with an antireflection layer made of a material containing a transition metal, and carries out a treatment of causing a highly concentrated ozone gas with a concentration of 50 to 100 vol % to act on the antireflection layer to thereby form a surface modified layer comprising a strong oxide film containing an oxide of the transition metal at a surface of the antireflection layer.

摘要翻译： 提供了一种制造掩模坯料的方法，该掩模坯料具有改进的耐臭氧清洁等的清洁性能，因此能够防止由于清洁而引起的掩模性能的劣化。 该方法用于制造掩模坯料，其在基板上具有在其表面形成有由含有过渡金属的材料制成的抗反射层的薄膜，并进行使高浓度的臭氧气体与 浓度为50〜100体积％，从而形成表面改性层，该表面改性层包含在抗反射层的表面含有过渡金属的氧化物的强氧化物膜。

公开(公告)号：US20150221659A1

公开(公告)日：2015-08-06

申请号：US14612613

申请日：2015-02-03

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Wensheng Wang

IPC分类号： H01L27/115 ,  H01L21/285 ,  H01L21/3213 ,  H01L49/02 ,  H01L21/02

CPC分类号： H01L27/11507 ,  H01L21/02197 ,  H01L21/02356 ,  H01L21/28568 ,  H01L21/3213 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

摘要： A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底上形成导电膜; 在导电膜上形成第一铁电体膜; 在所述第一铁电体膜上形成无定形第二铁电体膜; 在所述第二铁电体膜上形成含有钌的过渡金属氧化物材料膜; 在过渡金属氧化物材料膜上形成第一导电金属氧化物膜，而不将过渡金属氧化物材料膜暴露于空气中; 退火和结晶第二铁电薄膜; 以及对第一导电金属氧化物膜，第一铁电体膜，第二铁电体膜和导电膜进行图案化以形成铁电体电容器。

公开(公告)号：US20150179652A1

公开(公告)日：2015-06-25

申请号：US14639994

申请日：2015-03-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L27/11 ,  H01L21/28 ,  H01L21/3213

CPC分类号： H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

摘要： A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.

摘要翻译： 半导体器件的图案化结构包括至少第一图案化结构和至少第二图案化结构的衬底。 第一图案结构是单层结构，第二图案结构是多层结构。 第二图案化结构的宽度大于第一图案化结构的宽度。

公开(公告)号：US20150179531A1

公开(公告)日：2015-06-25

申请号：US14136449

申请日：2013-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Hsi Wu ,  Han-Wen Liao ,  Chih-Yu Lin ,  Cherng-Chang Tsuei

IPC分类号： H01L21/66 ,  H01L21/3213 ,  H01L21/683 ,  H01L21/02

CPC分类号： H01L22/12 ,  H01L21/02019 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/6831 ,  H01L22/20

摘要： A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.

摘要翻译： 用于图案化晶片的方法包括在晶片上执行第一图案化，并且在执行第一图案化之后，计算由于在晶片上执行第二图案化而预测晶片的临界尺寸的变化的模拟剂量映射器（DoMa）映射。 该方法还包括在晶片上执行第二图案化。 执行第二图案化包括根据模拟DoMa图与晶片的期望临界尺寸之间的差异来调整第二图案化的一个或多个蚀刻参数。

公开(公告)号：US09064848B2

公开(公告)日：2015-06-23

申请号：US14531650

申请日：2014-11-03

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Xiang Hu ,  Richard S. Wise ,  Habib Hichri ,  Catherine Labelle

IPC分类号： H01L21/3213 ,  H01L21/311 ,  H01L23/48 ,  H01L27/11 ,  H01L21/3105

CPC分类号： H01L23/48 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/3213 ,  H01L21/32139 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

摘要翻译： 在图案转印和后续短路过程中的抗反射残余物通过使用下面的牺牲层来确保完全去除抗反射层而消除。 实施例包括在导电层（例如硅衬底）上形成硬掩模层，在硬掩模层上形成牺牲层，在牺牲层上形成光学色散层，在光学色散上形成硅抗反射涂层 在硅抗反射涂层上形成光致抗蚀剂层，其中光致抗蚀剂层限定图案，蚀刻以将图案转移到硬掩模层，以及剥离至少光学色散层和牺牲层。

公开(公告)号：US20140259658A1

公开(公告)日：2014-09-18

申请号：US13924681

申请日：2013-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Hsiung HSU ,  Huang-Yu CHEN ,  Tsong-Hua OU ,  Wen-Hao CHEN

IPC分类号： H05K3/08

CPC分类号： G03F7/2022 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/3213 ,  H05K3/0005 ,  H05K3/0082 ,  H05K3/06 ,  H05K3/068 ,  H05K2201/09781 ,  H05K2203/0557 ,  H05K2203/1476 ,  Y10T29/49156

摘要： A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

摘要翻译： 一种方法包括用第一金属图案在衬底上图案化层; 在相对于所述基板的第一位置使用切割掩模，以执行用于从所述第一图案内的第一区域去除材料的第一切割图案; 并且使用相同的切割掩模在相对于衬底上的相同层的第二位置执行第二切割图案，用于从衬底上的相同层的第二金属图案中的第二区域去除材料。

公开(公告)号：US20140252445A1

公开(公告)日：2014-09-11

申请号：US13788174

申请日：2013-03-07

申请人： GLOBALFOUNDRIES SINGAPORE PTE. LTD.

发明人： Yu Chen ,  Huajun Liu ,  Siow Lee Chwa ,  Soh Yun Siah ,  Yanxia Shao ,  Yoke Leng Lim

IPC分类号： H01L21/283 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825

摘要： Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

摘要翻译： 公开了一种细长分裂栅极电池的制造和所得到的器件。 实施例包括在基板上形成第一栅极，第一栅极具有上表面和覆盖上表面的硬掩模，在第一栅极和硬掩模的侧表面上形成间隔隔离层，形成第二栅极 第一栅极的一侧，第二栅极的最上部点在第一栅极的上表面下方，去除硬掩模，在暴露的垂直表面上形成间隔物，并在第一和第二栅极的暴露表面上形成硅化物 。