公开(公告)号：US20170338164A1

公开(公告)日：2017-11-23

申请号：US15599492

申请日：2017-05-19

Applicant: Infineon Technologies AG

Inventor： Heinrich Koerner ,  Michael Bauer ,  Reimund Engl ,  Michael Huettinger ,  Werner Kanert ,  Joachim Mahler ,  Brigitte Ruehle

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/293 ,  H01L21/56 ,  H01L23/295 ,  H01L23/296 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48647 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2224/45664 ,  H01L2224/45644 ,  H01L2224/45669

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

公开(公告)号：US09576944B2

公开(公告)日：2017-02-21

申请号：US14959276

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC: H01L29/94 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract translation: 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US20170040431A1

公开(公告)日：2017-02-09

申请号：US15229828

申请日：2016-08-05

Applicant: Infineon Technologies AG

Inventor： Thomas Basler ,  Joachim Mahler ,  Hans-Joachim Schulze

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/861 ,  H01L29/43

CPC classification number: H01L29/861 ,  H01L29/0619 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/456 ,  H01L29/47 ,  H01L29/872

Abstract: A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure including an NTC (negative temperature coefficient of resistance) portion arranged adjacent to the at least one highly doped region at a front side surface of the semiconductor substrate. The NTC portion includes a negative temperature coefficient of resistance material.

Abstract translation: 半导体器件包括形成在半导体衬底中的电子器件布置的至少一个高度掺杂区域和包括在前侧表面上与所述至少一个高掺杂区域相邻布置的NTC（负电阻温度系数）部分的接触结构 的半导体衬底。 NTC部分包括电阻材料的负温度系数。

公开(公告)号：US20160358886A1

公开(公告)日：2016-12-08

申请号：US15171364

申请日：2016-06-02

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L23/44 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/071 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40228 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/831 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/848 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/9201 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/15151 ,  H01L2924/15153 ,  H05K7/023 ,  H05K7/08 ,  H05K7/10 ,  H05K7/20 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83

Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

Abstract translation: 半导体功率装置包括具有第一表面和与第一表面相对的第二表面的芯片载体。 半导体功率布置还包括附接到芯片载体的多个功率半导体芯片，其中功率半导体芯片倾斜于芯片载体的第一和/或第二表面。

公开(公告)号：US09443760B2

公开(公告)日：2016-09-13

申请号：US14543557

申请日：2014-11-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/13 ,  H01L23/433 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/07 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

Abstract translation: 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。

公开(公告)号：US20160240449A1

公开(公告)日：2016-08-18

申请号：US15095784

申请日：2016-04-11

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/29 ,  H01L23/495 ,  C25D13/12 ,  H01L21/48 ,  H01L21/56 ,  C25D13/06 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/293 ,  C25D13/06 ,  C25D13/12 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/573 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8492 ,  H01L2224/8592 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/284 ,  H05K2203/135 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Abstract translation: 公开了封装组件和制造封装组件的方法。 在一个实施例中，封装部件包括具有部件载体接触件和设置在部件载体上的部件的部件载体，该部件具有部件接触。 封装部件还包括将部件载体接触件与部件接触件连接的导电连接元件，直接设置在部件或导电连接元件的顶表面中的至少一个上的绝缘膜，以及封装部件载体的密封剂， 组件和封闭的导电连接元件。

公开(公告)号：US20160064298A1

公开(公告)日：2016-03-03

申请号：US14835750

申请日：2015-08-26

Applicant: Infineon Technologies AG

Inventor： Peh Hean TEH ,  Jagen Krishnan ,  Swee Kah Lee ,  Poh Cheng Lim ,  Joachim Mahler ,  Chew Theng Tai ,  Yik Yee Tan ,  Soon Lock Goh

IPC: H01L23/29 ,  H01L21/3105 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L21/3105 ,  C09J163/00 ,  H01L21/56 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8392 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and a plurality of capsules in the encapsulant, wherein the capsules comprise a core comprising an additive and comprise a shell, in particular a crackable shell, enclosing the core.

Abstract translation: 一种电子设备，包括具有安装表面的载体，安装在所述安装表面上的至少一个电子芯片，至少部分地封装所述载体和所述至少一个电子芯片的密封剂以及所述密封剂中的多个胶囊，其中所述胶囊 包括包含添加剂的芯，并且包括封装芯的壳，特别是可裂纹壳。

公开(公告)号：US09190389B2

公开(公告)日：2015-11-17

申请号：US13951554

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/02 ,  H01L25/04 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01L23/538

CPC classification number: H01L25/04 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.

Abstract translation: 芯片封装器件包括导电芯片载体，至少一个连接到导电芯片载体的半导体芯片，以及嵌入芯片载体，至少一个半导体芯片和无源电子器件的绝缘叠层结构。 无源电子器件包括第一结构导电层，第一结构化导电层在层压结构的表面上延伸。

公开(公告)号：US09165792B2

公开(公告)日：2015-10-20

申请号：US13625893

申请日：2012-09-25

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Anton Mauder

IPC: H01L23/48 ,  H01L21/50 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27416 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/80203 ,  H01L2224/80801 ,  H01L2224/80893 ,  H01L2224/80894 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area.

Abstract translation: 提供集成电路，集成电路包括：载体，其包括至少一个电子部件和布置在载体的第一侧上的至少一个接触区域，其中至少一个电子部件电连接到该至少一个触点 区; 与所述载体的第一侧接合的无机材料层晶片，其中所述载体具有第一热膨胀系数，并且其中所述无机材料层具有第二热膨胀系数，其中所述第二热膨胀系数具有 与第一热膨胀系数相比低于100％; 以及通过无机材料层形成的至少一个接触孔，其中所述至少一个接触通孔接触所述至少一个接触区域。

公开(公告)号：US09142739B2

公开(公告)日：2015-09-22

申请号：US13921060

申请日：2013-06-18

Applicant: Infineon Technologies AG

Inventor： Andreas Eder ,  Henrik Ewe ,  Stefan Landau ,  Joachim Mahler

IPC: H01L33/56 ,  H01L33/54 ,  H01L33/62 ,  H01L23/00

CPC classification number: H01L33/56 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2933/0066 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method and a system for a reliable LED semiconductor device are provided. In one embodiment, the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.

Abstract translation: 提供了一种用于可靠的LED半导体器件的方法和系统。 在一个实施例中，该装置包括载体，设置在载体上的发光二极管，设置在发光二极管和载体上的封装材料，形成在封装材料中的至少一个贯穿连接，以及设置和结构化的金属化层 通过至少一个通过连接。