Abstract:
A structure provides for the control of bond wire impedance. In an example embodiment, there is an integrated circuit device comprising a semiconductor device die having a plurality of grounding pads, signal pads, and power pads and a package for mounting the integrated circuit and includes a conductive path having at least one reference trace that surrounds the integrated circuit. A grounding arch is disposed over the semiconductor device die.
Abstract:
An integrated circuit device comprising an integrated circuit die mounted on a leadframe having a plurality of inner leads. The integrated circuit die has a plurality of bond pads that are electrically connected to the inner leads of the leadframe, wherein at least two bond pads are connected to a one of the plurality of inner leads and/or at least two inner leads are connected to one or more bond pads with a single bond wire. A single bond wire is connected to a first bond pad or inner lead and subsequently wedge or stitch bonded to a second bond pad or inner lead, then it is connected to a third bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and inner lead(s). The bond pad(s) of the die and inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.
Abstract:
A semiconductor device is formed from a die and a lead frame having one or more bus bars. Portions of the bus bars are overlain with an electrically insulative material while leaving bonding areas unobstructed, whereby bond wires which span the bus bar(s) may be bonded with a shorter wire and a lower loop, without the danger of shorting to the bus bar(s). The incidence of harmful wire sweep in the encapsulation step is also reduced.
Abstract:
The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.
Abstract:
An apparatus and method of forming improved wire bonds between the contact pads on semiconductor devices and individual lead frame fingers of a lead frame. The apparatus and method include the use of a penetrating individual independent lead finger clamp during the wire bonding process to provide increased stability of the individual lead finger for improved bonding by the clamp penetrating a portion of the lead finger being bonded. If desired, the apparatus and method also provide for the use of either a penetrating or non-penetrating fixed clamp for the lead fingers during the wire bonding process in addition to the penetrating individual independent lead finger clamp during the wire bonding process to provide increased stability of the individual lead finger for improved bonding.
Abstract:
A die structure of a package is provided. The die structure of the package includes a carrier and a die. The die includes a first portion and a second portion. The top surface of the first portion is an active surface. The second portion is configured below the first portion. A first width of the first portion is smaller than a second width of the second portion. And the second portion of the die is adhered to the carrier.
Abstract:
Contact structures are formed by building a core structure on a substrate and over coating the core structure with a material that is harder or has a greater yield strength than the material of the core structure. The core structure may be formed by attaching a wire to the substrate and spooling the wire out from a spool. While spooling the wire out, the spool may be moved to impart a desired shape to the wire. The wire is severed from the spool and over coated. As an alternative, the wire is not over coated. The substrate may be an electronic device, such as a semiconductor die.
Abstract:
In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.
Abstract:
An integrated circuit having copper interconnecting metallization (311, 312) protected by a first, inorganic overcoat layer (320), portions of the metallization exposed in windows (301, 302) opened through the thickness of the first overcoat layer. A patterned conductive barrier layer (330) is positioned on the exposed portion of the copper metallization and on portions of the first overcoat layer surrounding the window. A bondable metal layer (350, 351) is positioned on the barrier layer; the thickness of this bondable layer is suitable for wire bonding. A second, organic overcoat layer (360) is surrounding the window so that the surface (360a) of this second overcoat layer at the edge of the window is at or above the surface (350a) of the bondable layer. The second overcoat layer may be spaced (370) from the edge of the bondable metal layer.
Abstract:
The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devices 30A, 31A, 32, 33A, 34A and 38. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire.These semiconductor devices have a plurality of circuit elements as one package, so that the mounting operation on the mounting board can be significantly reduced.