公开(公告)号：US09748272B2

公开(公告)日：2017-08-29

申请号：US13452836

申请日：2012-04-21

Applicant: Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber

IPC: H01L29/20 ,  H01L21/20 ,  H01L23/36 ,  H01L33/12 ,  H01L27/12 ,  H01L21/78 ,  H01L21/84 ,  H01L23/367 ,  H01L29/786 ,  H01L21/762 ,  H01L23/00

CPC classification number: H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a strain inducing material is deposited on the excavated insulator region. The strain inducing material interacts with the pattern of excavated insulator such that a single layer provides both tensile and compressive stress to p-channel and n-channel transistors, respectively. In alternative embodiments, the entire substrate is removed before forming the strain inducing material.

公开(公告)号：US09728490B2

公开(公告)日：2017-08-08

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

公开(公告)号：US20170221861A1

公开(公告)日：2017-08-03

申请号：US15485104

申请日：2017-04-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

IPC: H01L25/065 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/0217 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2224/05552

Abstract: A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a protruding end of the TSV protruding from a second side of the device substrate. A liner covers the sidewall of the first conductive material from a below the top surface of the protruding end of the TSV to an opposite end of the TSV. A passivation layer is disposed over the second side of the device substrate and over a portion of the liner disposed on the protruding end of the TSV, the passivation layer having a stair-step surface extending away from the TSV. A conductive interface layer is disposed over the passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the TSV. A second conductive material is disposed over the first conductive material.

公开(公告)号：US09721935B2

公开(公告)日：2017-08-01

申请号：US14475298

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazushige Kawasaki ,  Yoichiro Kurita

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/80203 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/80001 ,  H01L2224/81 ,  H01L2924/014

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

公开(公告)号：US20170154857A1

公开(公告)日：2017-06-01

申请号：US15430582

申请日：2017-02-13

Applicant: Infineon Technologies AG

Inventor： Srinivasa Reddy Yeduru ,  Karl Heinz Gasser ,  Stefan Woehlert ,  Karl Mayer ,  Francisco Javier Santos Rodriguez

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L21/288 ,  H01L21/4814 ,  H01L21/6835 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/04026 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/27002 ,  H01L2224/27005 ,  H01L2224/2732 ,  H01L2224/2747 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29021 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29393 ,  H01L2224/32245 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05124 ,  H01L2224/05187 ,  H01L2924/0665 ,  H01L2924/01006 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/07802

Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

公开(公告)号：US09653430B2

公开(公告)日：2017-05-16

申请号：US14955124

申请日：2015-12-01

Applicant: Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

Inventor： Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/03616 ,  H01L2224/0392 ,  H01L2224/04 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14515 ,  H01L2224/16146 ,  H01L2224/73251 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/00012 ,  H01L22/00 ,  H01L21/304 ,  H01L2221/68304 ,  H01L2221/68381 ,  H01L21/78

Abstract: Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

公开(公告)号：US20170047300A1

公开(公告)日：2017-02-16

申请号：US15340909

申请日：2016-11-01

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/768 ,  H01L23/48 ,  H01L21/268

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract translation: 芯片封装包括芯片，第一通孔，激光停止结构，第一隔离层，第二通孔和导电层。 第一通孔从芯片的第二表面延伸到第一表面以暴露导电焊盘，并且激光器停止结构设置在由第一通孔暴露的导电焊盘上，激光停止结构的上表面 在第二个表面之上。 第一隔离层覆盖第二表面和激光停止结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光停止结构，并且导电层在第三表面上并延伸到第二通孔中以接触激光停止结构。

公开(公告)号：US20170005080A1

公开(公告)日：2017-01-05

申请号：US15268742

申请日：2016-09-19

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Yoshinori DEGUCHI ,  Fumikazu TAKEI ,  Akio HASEBE ,  Naohiro MAKIHIRA ,  Mitsuyuki KUBO

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/544 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L22/12 ,  H01L22/14 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2223/54493 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/11009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract translation: 当存储器芯片安装在逻辑芯片上时，将形成在逻辑芯片的背面的识别标记的识别范围成像，识别范围的形状，逻辑芯片的多个凸点与 基于识别的结果执行上述存储芯片的多个投影电极，并且将上述存储芯片安装在逻辑芯片上。 此时，识别范围的形状与凸块的阵列形状的任何部分不同，结果，可以可靠地识别识别范围形状的识别标记，并且逻辑的凸块的对准 高精度地执行上述存储芯片的芯片和投影电极。

公开(公告)号：US20170004990A1

公开(公告)日：2017-01-05

申请号：US15112429

申请日：2014-03-19

Applicant: Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

Inventor： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/6836 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5446 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/304 ,  H01L2221/68363 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/03 ,  H01L2224/85

Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

Abstract translation: 提供制造半导体器件的方法。 根据该方法，第一胶合层，第一剥离层，第二胶层和第二剥离层可以顺序插入载体和器件晶片之间。 所有第一胶合层，第一释放层，第二胶层和第二剥离层可以由热固性树脂形成。

公开(公告)号：US20160372512A1

公开(公告)日：2016-12-22

申请号：US14902085

申请日：2014-04-30

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Heui Gyun AHN

IPC: H01L27/146 ,  H01L21/683

CPC classification number: H01L27/14687 ,  H01L21/6835 ,  H01L24/02 ,  H01L24/03 ,  H01L24/92 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0231 ,  H01L2224/03002 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2221/683 ,  H01L21/304 ,  H01L21/76898 ,  H01L2224/03

Abstract: The present invention relates to a technology for simply performing a process of forming a pad on the rear surface of a via hole in a packing process in a process of forming a pad of a wafer. The present invention is characterized by a packing process in a process for manufacturing a wafer, the packing process comprising the steps of: attaching glass to the upper portion of a micro lens and then separating a handling wafer from an element wafer, thereby exposing metal layers formed on the element wafer to the outside; and forming pads for the metal layers.

Abstract translation: 本发明涉及一种用于在形成晶片垫的过程中在包装过程中简单地执行在通孔的后表面上形成焊盘的工艺的技术。 本发明的特征在于在制造晶片的过程中的包装过程，所述包装过程包括以下步骤：将玻璃附着到微透镜的上部，然后将处理晶片与元件晶片分离，由此暴露金属层 在元件晶片上形成到外部; 以及用于金属层的成形垫。