公开(公告)号：US20150221584A1

公开(公告)日：2015-08-06

申请号：US14173147

申请日：2014-02-05

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Johathan A. Noquil

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

摘要： A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

摘要翻译： 电源系统（200）具有带导线和焊盘（201，开关节点端子）的QFN引线框架; 垫表面，其具有凹入深度（270）的部分和适合于附接半导体芯片的轮廓。 第一FET芯片（220）垂直地堆叠到相对的焊盘表面。 夹子（240）垂直堆叠在第一FET芯片上并连接到引线（202，接地输出端子）。 第二FET芯片（210）的源极端子连接到凹部，其漏极（210a，输入端子）和栅极（210b）端子与未凹入部分共面。 驱动器和控制器芯片（230）附接到夹子。 包装化合物（290）封装部件但留下焊盘表面，并且第二FET芯片的漏极和栅极端子未封装。

公开(公告)号：US20150069637A1

公开(公告)日：2015-03-12

申请号：US14031000

申请日：2013-09-18

申请人： Broadcom Corporation

发明人： Sam Ziqun ZHAO ,  Rezaur Rahman KHAN

IPC分类号： H01L23/00

CPC分类号： H01L24/17 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/30131 ,  H01L2224/30141 ,  H01L2224/30179 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

摘要翻译： 集成电路（IC）封装包括具有第一表面和与第一表面相对的第二表面的IC管芯。 IC封装包括耦合到IC管芯的第二表面的第一接触构件。 IC封装包括具有第一表面和与第一表面相对的第二表面的底部衬底，其中底部衬底的第一表面经由第一接触构件联接到IC管芯的第二表面。 IC封装包括通过粘合剂材料耦合到IC管芯的第一表面的插入器基板，其中粘合材料设置在中介层基板的至少一个表面上。 IC封装包括沿着插入器衬底的周边耦合的第二接触构件，其中插入器衬底经由第二接触构件联接到底部衬底的第一表面。

公开(公告)号：US20150049450A1

公开(公告)日：2015-02-19

申请号：US14455204

申请日：2014-08-08

申请人： FUJITSU LIMITED

发明人： Keishiro Okamoto ,  Seiki Sakuyama

IPC分类号： H05K1/18 ,  B23K1/20 ,  H05K3/34

CPC分类号： H05K1/181 ,  B23K1/20 ,  H01L21/50 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/171 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/75252 ,  H01L2224/75745 ,  H01L2224/81007 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/92 ,  H01L2224/9221 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/0271 ,  H05K3/303 ,  H05K3/305 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

摘要： An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.

摘要翻译： 电子设备包括：第一电子部件; 第一构件，其设置在第一电子部件的第一表面上，并且包括被配置为相对于第一表面对角地面对的外表面; 设置在所述第一表面上方的第二电子部件; 第二构件，其对应于第二电子部件的面对第一表面的第二表面上的第一构件，并且包括构造成相对于第二表面对角地向下面并且构造成面向外表面的内表面; 以及设置在第一表面和第二表面之间并且电连接第一电子部件和第二电子部件的焊料。

公开(公告)号：US20140170813A1

公开(公告)日：2014-06-19

申请号：US14094431

申请日：2013-12-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd. ,  IMEC

发明人： Yu-Hsiang Hu ,  Chung-Shi Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81012 ,  H01L2224/81047 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8183 ,  H01L2224/81948 ,  H01L2224/81986 ,  H01L2224/83047 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9221 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552

摘要： A method is provided for bonding a first semiconductor substrate to a second semiconductor substrate using low temperature thermo-compression. The bonding method comprises the step of in-situ mechanically scrubbing the metal contact structure surfaces prior to thermo-compression bonding step, thereby planarizing the removing the oxides and/or contaminants from the metal contact structure surfaces. The thermo-compression bonding step is followed by a thermal annealing step for creating interface diffusion between the metal contact structure of the first and second semiconductor substrates

摘要翻译： 提供了一种使用低温热压将第一半导体衬底接合到第二半导体衬底的方法。 接合方法包括在热压接步骤之前对金属接触结构表面进行原位机械洗涤的步骤，从而平坦化从金属接触结构表面去除氧化物和/或污染物。 热压接步骤之后是用于在第一和第二半导体衬底的金属接触结构之间产生界面扩散的热退火步骤。

公开(公告)号：US08686299B2

公开(公告)日：2014-04-01

申请号：US13382368

申请日：2010-05-26

申请人： Koji Motomura ,  Seiichi Yoshinaga ,  Tadahiko Sakai

发明人： Koji Motomura ,  Seiichi Yoshinaga ,  Tadahiko Sakai

IPC分类号： H05K1/16 ,  H05K3/34 ,  H05K3/30

CPC分类号： H05K3/305 ,  H01L21/563 ,  H01L23/295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/98 ,  H01L2224/0401 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17135 ,  H01L2224/17179 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/33179 ,  H01L2224/73203 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/8121 ,  H01L2224/8159 ,  H01L2224/81599 ,  H01L2224/81609 ,  H01L2224/81611 ,  H01L2224/81613 ,  H01L2224/81616 ,  H01L2224/81639 ,  H01L2224/81644 ,  H01L2224/81647 ,  H01L2224/81815 ,  H01L2224/81855 ,  H01L2224/81905 ,  H01L2224/83104 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8321 ,  H01L2224/8359 ,  H01L2224/83599 ,  H01L2224/83609 ,  H01L2224/83611 ,  H01L2224/83613 ,  H01L2224/83616 ,  H01L2224/83639 ,  H01L2224/83644 ,  H01L2224/83647 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/225 ,  H05K3/3436 ,  H05K2203/0425 ,  H05K2203/176 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： An electronic element unit (1) includes an electronic element (2) having a plurality of connecting terminals (12) on a lower surface thereof, a circuit board (3) having a plurality of electrodes (22) corresponding to the connecting terminals (12) on an upper surface thereof. The connecting terminals (12) and the electrodes (22) are connected by solder bumps (23), and the electronic element (2) and the circuit board (3) are partly bond by a resin bond part (24) made of a thermosetting material of a thermosetting resin, and a metal powder (25) is included in the resin bond parts (24) in a dispersed state. The metal powder (25) has a melting point lower than a temperature at which the resin bond parts (24) are heated when a work (a repairing work) is carried out for removing the electronic element (2) from the circuit board (3).

摘要翻译： 电子元件单元（1）包括在其下表面上具有多个连接端子（12）的电子元件（2），具有对应于连接端子（12）的多个电极（22）的电路板（3） ）在其上表面。 连接端子（12）和电极（22）通过焊锡凸块（23）连接，电子元件（2）和电路板（3）通过由热固性树脂制成的树脂粘接部分（24） 热固性树脂的材料和金属粉末（25）以分散状态包含在树脂粘合部分（24）中。 当进行从电路板（3）移除电子元件（2）的工件（修理作业）时，金属粉末（25）的熔点低于加热树脂接合部分（24）的温度 ）。

公开(公告)号：US20110175237A1

公开(公告)日：2011-07-21

申请号：US13056462

申请日：2009-11-06

申请人： Yoshihiro Tomura ,  Kazumichi Shimizu ,  Kentaro Kumazawa

发明人： Yoshihiro Tomura ,  Kazumichi Shimizu ,  Kentaro Kumazawa

IPC分类号： H01L23/48 ,  H01L21/50 ,  B29C65/20

CPC分类号： H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/1134 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75303 ,  H01L2224/75313 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/9221 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3512

摘要： A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.

摘要翻译： 将半导体芯片（1）倒装安装在电路板（4）上，其中底部填充树脂（6）插入在半导体芯片（1）和电路板（4）之间以及覆盖半导体芯片（1）的容器中， 被接合在电路板（4）上。 此时，通过压接工具（8）对设置在电路基板（4）与半导体芯片（1）之间的底部填充树脂（6）的半导体芯片（1）进行加压加压。 同时，通过压接工具（8）以周期性重复的图案形成有表面凹凸的膜（13），将半导体芯片（1）周围突出的底部填充树脂（6）的表面按压 形成表面凹凸（16a）。 覆盖半导体芯片（1）的容器的内表面与底部填充树脂的表面上的表面凹凸（16a）接合。

公开(公告)号：US20110031596A1

公开(公告)日：2011-02-10

申请号：US12535963

申请日：2009-08-05

申请人： Mike D. Gruenhagen ,  James J. Murphy ,  Suku Kim ,  Jim Pierce ,  William S. Beggs ,  Thomas P. Welch

发明人： Mike D. Gruenhagen ,  James J. Murphy ,  Suku Kim ,  Jim Pierce ,  William S. Beggs ,  Thomas P. Welch

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/488 ,  B23K35/22

CPC分类号： B23K35/0238 ,  B23K35/262 ,  B23K35/3033 ,  B23K35/325 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/14181 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  Y10T428/12222 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2224/03 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds or alloys and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit, a contact layer contacting the substrate, a TiNi-containing soldering layer on the contact layer, an oxidation prevention layer on the soldering layer, a solder bump on the soldering layer, and a lead frame or PCB attached to the solder bump. The combination of the Ti and Ni materials in the soldering layer exhibits many features not found in the Ti and Ni materials alone, such as reduced wafer warpage, increased ductility for improved elasticity, decreased consumption of the Ni in the soldering layer, and decreased manufacturing costs. Other embodiments are described.

摘要翻译： 描述了包含镍钛（NiTi或TiNi）化合物或合金的半导体器件及其制造方法。 这些器件包含具有集成电路的硅衬底，与衬底接触的接触层，接触层上的含TiNi的焊接层，焊接层上的氧化防止层，焊接层上的焊料凸块和引线框架 或PCB连接到焊料凸块。 Ti和Ni材料在焊接层中的组合在单独的Ti和Ni材料中显示出许多特征，例如减少晶片翘曲，提高延展性以改善弹性，降低焊接层中的Ni消耗以及减少制造 费用 描述其他实施例。

公开(公告)号：US20080286904A1

公开(公告)日：2008-11-20

申请号：US12153378

申请日：2008-05-16

申请人： Jing Li Yuan ,  Jae Cheon Doh ,  Tae Hoon Kim ,  Si Joong Yang ,  Seung Wook Park

发明人： Jing Li Yuan ,  Jae Cheon Doh ,  Tae Hoon Kim ,  Si Joong Yang ,  Seung Wook Park

IPC分类号： H01L21/60

CPC分类号： H03H9/1092 ,  H01L23/10 ,  H01L24/14 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/17515 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/301 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83193 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.

摘要翻译： 提供一种半导体封装的制造方法。 在该方法中，设置用于盖基板的晶片。 用于盖基板的晶片在下表面上包括多个通孔和通孔电极。 提供了用于器件衬底的晶片。 用于器件衬底的晶片包括上表面上的电路单元和连接电极。 用于盖衬底的晶片和用于器件衬底的晶片主要通过主要粘合剂的介质粘合。 形成沟槽，以将器件基板的晶片的上表面沿初级粘合剂的外边缘暴露于外部。 通过二次粘合剂的介质进行二次接合操作，以电连接通孔电极和连接电极。 用于器件衬底的晶片沿虚拟切割线切割。

公开(公告)号：US20180331022A1

公开(公告)日：2018-11-15

申请号：US15948190

申请日：2018-04-09

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Reyn QIN ,  Lucy FAN ,  Meifang SONG ,  Xiaoli WANG

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/13

CPC分类号： H01L23/49517 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/291 ,  H01L2224/32058 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/37012 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83907 ,  H01L2224/84345 ,  H01L2224/84385 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/84

摘要： A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.

公开(公告)号：US09991184B2

公开(公告)日：2018-06-05

申请号：US14648636

申请日：2013-05-28

申请人： SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

发明人： Kosuke Ikeda

IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L23/42 ,  H01L23/051 ,  H01L23/00 ,  H01L25/07 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/055 ,  H01L23/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/373 ,  H01L21/50

CPC分类号： H01L23/3672 ,  H01L21/4817 ,  H01L21/50 ,  H01L21/565 ,  H01L23/051 ,  H01L23/055 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49866 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1318 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16237 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/8348 ,  H01L2224/83815 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/92247 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1611 ,  H01L2924/16152 ,  H01L2924/16724 ,  H01L2924/1679 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01042 ,  H01L2924/01074

摘要： An electronic module 1 includes an electronic module 10 that includes a substrate 11 and an electronic element 12, an electronic module 20 that includes a substrate 21 arranged such that the principal surface 21a faces the principal surface 11a, an electronic element 22 electrically connected to the electronic element 12 with a connecting member 18 therebetween, and an electronic element 23 electrically connected to the electronic element 12 with a connecting member 19 therebetween passing through the substrate 21 in a thickness direction, the electronic module 20 thermally connected to the electronic module 10 by the connecting members 18 and 19, and a heat sink 30 that includes a housing part 31a therein and houses the electronic modules 10 and 20 in the housing part 31a such that the principal surface 11b is in contact with an inner wall surface of the housing part 31a.