公开(公告)号：US08338288B2

公开(公告)日：2012-12-25

申请号：US13081160

申请日：2011-04-06

申请人： Tamaki Wada ,  Akihiro Tobita ,  Seiichi Ichihara

发明人： Tamaki Wada ,  Akihiro Tobita ,  Seiichi Ichihara

IPC分类号： H01L21/44

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01063 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.

摘要翻译： 关于其中导电构件耦合到从形成在钝化膜中的开口露出的接合焊盘的表面的半导体器件，提供了能够抑制钝化膜中的裂纹的发生的技术。 电极层的第一端和焊盘的第一端之间的第二平面距离大于电极层的第一端和开口的第一端之间的第一平面距离。 由于电极层的第一端和焊盘的第一端之间的第二平面距离长，所以即使当电极的耦合位置偏离电极层的第一端侧时，由于将电线耦合到 可以防止电极层的台阶部分传递到焊盘的第一端部。

公开(公告)号：US08324511B1

公开(公告)日：2012-12-04

申请号：US12754837

申请日：2010-04-06

申请人： Ronald Patrick Huemoeller ,  Frederick Evans Reed ,  David Jon Hiner ,  Kiwook Lee

发明人： Ronald Patrick Huemoeller ,  Frederick Evans Reed ,  David Jon Hiner ,  Kiwook Lee

IPC分类号： H05K1/11

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2924/00014 ,  H05K3/4038 ,  H05K3/42 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method includes applying a backside passivation layer to an inactive surface of an electronic component and to enclose a through via nub protruding from the inactive surface. The method further includes laser ablating the backside passivation layer to reveal a portion of the through via nub. The backside passivation layer is formed of a low cost organic material. Further, by using a laser ablation process, the backside passivation layer is removed in a controlled manner to reveal the portion of the through via nub. Further, by using a laser ablation process, the resulting thickness of the backside passivation layer is set to a desired value in a controlled manner. Further, by using a laser ablation process, the fabrication cost is reduced as compared to the use of chemical mechanical polish.

摘要翻译： 一种方法包括将背面钝化层施加到电子部件的非活性表面并且包围从非活性表面突出的通孔。 该方法还包括激光烧蚀背面钝化层以露出通孔的一部分。 背面钝化层由低成本的有机材料形成。 此外，通过使用激光烧蚀工艺，以受控的方式去除背面钝化层以露出通孔的部分。 此外，通过使用激光烧蚀工艺，将所得到的背面钝化层的厚度以受控的方式设定为期望值。 此外，通过使用激光烧蚀工艺，与使用化学机械抛光相比，制造成本降低。

公开(公告)号：US08304766B2

公开(公告)日：2012-11-06

申请号：US13094780

申请日：2011-04-26

申请人： Mou-Shiung Lin ,  Huei-Mei Yen ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Huei-Mei Yen ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Ke-Hung Chen

IPC分类号： H01L23/58 ,  H01L21/00

CPC分类号： H01L24/11 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/11912 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

摘要翻译： 半导体芯片包括由钝化层中的开口暴露的金属焊盘，其中金属焊盘具有测试区域和接合区域。 在测试步骤中，测试探头与测试区域接触进行电气测试。 在测试步骤之后，在测试区域上形成由测试探针产生的探针标记的聚合物层。 或者，半导体芯片包括分别由钝化层中的两个开口露出的测试焊盘和接合焊盘，其中测试焊盘连接到焊盘。 在测试步骤中，测试探针与测试垫接触进行电气测试。 在测试步骤之后，在测试垫上形成由测试探针产生的探针标记的聚合物层。

公开(公告)号：US08294279B2

公开(公告)日：2012-10-23

申请号：US11307127

申请日：2006-01-24

申请人： Ke-Hung Chen ,  Shih-Hsiung Lin ,  Mou-Shiung Lin

发明人： Ke-Hung Chen ,  Shih-Hsiung Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83051 ,  H01L2224/83365 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01007 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/29099

摘要： A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

摘要翻译： 一种组装芯片的方法。 提供第一芯片和第二芯片。 在第一芯片上形成至少一个导电柱，并且在导电柱上形成导电连接材料。 第二芯片还包括至少一个导电柱。 第一芯片经由导电柱和导电连接材料连接到第二芯片。

公开(公告)号：US20120248605A1

公开(公告)日：2012-10-04

申请号：US13404715

申请日：2012-02-24

申请人： Toshihide YAMAGUCHI

发明人： Toshihide YAMAGUCHI

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047

摘要： A semiconductor device includes an electrode (electrode pad), an insulation film (for example, protective resin film) formed over the electrode and having an opening for exposing the electrode. The semiconductor device further includes an under bump metal (UBM layer) formed over the insulation film and connected by way of the opening 5a to the electrode, and a solder ball formed over the under bump metal. In the under bump metal, a thickness A for the first portion situated in the opening above the electrode and the thickness B for the second portion situated in the under bump metal at the periphery of the opening over the insulation film are in a condition: A/B≧1.5, and the opening and the solder ball are in one to one correspondence.

摘要翻译： 半导体器件包括电极（电极焊盘），形成在电极上并具有用于使电极露出的开口的绝缘膜（例如，保护树脂膜）。 半导体器件还包括形成在绝缘膜上并通过开口5a连接到电极的下凸块金属（UBM层），以及形成在凸块下金属之上的焊球。 在凸块下金属中，位于电极上方的开口中的第一部分的厚度A和位于绝缘膜上的开口周边的位于凸块下部的第二部分的厚度B处于以下条件：A /B≥1.5，开口和焊球一一对应。

公开(公告)号：US20120241951A1

公开(公告)日：2012-09-27

申请号：US13492397

申请日：2012-06-08

申请人： Kunzhong (Kevin) Hu ,  Edward Law

发明人： Kunzhong (Kevin) Hu ,  Edward Law

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/82

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552

摘要： Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.

摘要翻译： 提供了用于在芯片/晶片上印刷凹凸金属化（UBM）特征的方法，系统和装置。 接收具有由多个集成电路区域限定的表面的晶片。 每个集成电路区域具有钝化层，并且晶片表面上的多个端子可通过钝化层中的开口进入。 多个UBM特征以墨的形式形成在晶片的表面上，使得每个UBM特征形成为与多个端子的相应端子电耦合。 可以使用喷墨打印机以UBM特征的形式打印墨水。 UBM特征可以直接形成在对应的终端上，或者在耦合到相应终端的路由上形成。 可以在UBM特征上形成凸块互连。

公开(公告)号：US20120211900A1

公开(公告)日：2012-08-23

申请号：US13031546

申请日：2011-02-21

申请人： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

发明人： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

摘要： A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

摘要翻译： 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US08212362B2

公开(公告)日：2012-07-03

申请号：US12603106

申请日：2009-10-21

申请人： Kiyonori Watanabe

发明人： Kiyonori Watanabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05027 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.

摘要翻译： 半导体器件包括：半导体芯片，其具有第一主表面，具有处于暴露状态的电极焊盘;以及层间绝缘层，形成在第一主表面上，使得电极焊盘部分露出; 包括布线图案的重新配线层，所述布线图案具有线状部分，所述线状部分具有与所述电极焊盘电连接并从所述电极焊盘延伸的一个端部，以及连接到所述电极焊盘的另一端部的柱电极安装部分 直线部分 形成在所述柱状电极安装部上并具有与所述柱状电极安装部的上部轮廓相交的轮廓的底面的两个以上的立柱电极; 设置为使得所述柱电极的顶部露出的密封部; 以及形成在柱状电极的顶部上的外部端子。

公开(公告)号：US20120133379A1

公开(公告)日：2012-05-31

申请号：US13012916

申请日：2011-01-25

申请人： You-Hua CHOU ,  Mill-Jer WANG ,  Pi-Huang LEE ,  Jeff WANG ,  Feynmann CHU

发明人： You-Hua CHOU ,  Mill-Jer WANG ,  Pi-Huang LEE ,  Jeff WANG ,  Feynmann CHU

IPC分类号： G01R27/08 ,  H01L23/544

CPC分类号： G01R31/048 ,  H01L22/34 ,  H01L24/14 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

摘要翻译： 上述实施例提供了用于凸块电阻率测量的机构。 通过在模具的一个或多个角上使用指定的凸块，可以测量凸块的电阻率而不损坏装置并且没有定制的探测卡。 此外，可以在整个晶片上收集隆起电阻率。 收集的电阻率数据可用于监测用于形成凸块及其下层的工艺的稳定性和/或健康状况。

公开(公告)号：US20120119363A1

公开(公告)日：2012-05-17

申请号：US13357146

申请日：2012-01-24

申请人： Mukta G. Farooq

发明人： Mukta G. Farooq

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/013

摘要： Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature.

摘要翻译： 使用金属添加到Sn基无铅C4球以提高可靠性。 具体地说，在Sn中溶解度低的金属以相当于原子浓度小于1％的少量加入。 由于添加的金属的溶解度低，在C4球的固化期间形成微细的析出物，其作为在固化的C4球中形成多个晶粒的成核位置。 微细的沉淀物也通过堵塞晶界抑制快速的晶粒生长，并且作为在C4球中钉扎位错的试剂。 晶粒边界使得能够在半导体芯片和C4球的封装的热循环期间减轻应力的晶界滑动。 此外，微细沉淀物由于其固着性而防止沿着晶界的电迁移。