公开(公告)号：US20150123293A1

公开(公告)日：2015-05-07

申请号：US14597534

申请日：2015-01-15

申请人： Invensas Corporation

发明人： Wael Zohni ,  Chung-Chuan Tseng

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/0655 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3157 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge.

摘要翻译： 微电子组件可以包括具有在基板的第一和第二相对面对的表面之间延伸的开口的基板，该开口在第一方向上伸长; 以及至少一个微电子元件，其具有面向并连接到所述基板的第一表面的正面和在所述开口的上方的前表面处的多个触点，所述微电子元件具有远离所述前表面延伸的第一和第二相对的周边边缘。 第一周边边缘在开口的内边缘延伸超过第一方向或与第一方向对齐，并且开口延伸超出第二周边边缘。

公开(公告)号：US20150035141A1

公开(公告)日：2015-02-05

申请号：US14447415

申请日：2014-07-30

申请人： Amkor Technology, Inc.

发明人： Jin Seong Kim ,  Byong Woo Cho ,  Cha Gyu Song

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.

摘要翻译： 半导体管芯封装包括半导体管芯，用于改善与半导体管芯的第一面接合的模具翘曲的膜，形成在半导体管芯的第二面上的多个导电凸块， 半导体管芯的第二面被接合以电连接半导体管芯和衬底，以及施加这些部件的模具化合物，以形成与膜的暴露表面共面的半导体管芯封装的暴露表面。

公开(公告)号：US08865489B2

公开(公告)日：2014-10-21

申请号：US12778588

申请日：2010-05-12

申请人： John A. Rogers ,  Ralph Nuzzo ,  Hoon-sik Kim ,  Eric Brueckner ,  Sang Il Park ,  Rak Hwan Kim

发明人： John A. Rogers ,  Ralph Nuzzo ,  Hoon-sik Kim ,  Eric Brueckner ,  Sang Il Park ,  Rak Hwan Kim

IPC分类号： H01L31/0304 ,  H01L33/00 ,  H01L23/00 ,  H01L25/075 ,  H01L33/62

CPC分类号： H01L25/0753 ,  H01L21/6835 ,  H01L24/83 ,  H01L24/95 ,  H01L25/50 ,  H01L33/0079 ,  H01L33/32 ,  H01L33/486 ,  H01L33/507 ,  H01L33/54 ,  H01L33/62 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/8312 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2224/95085 ,  H01L2924/01322 ,  H01L2924/05432 ,  H01L2924/06 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2933/0041 ,  H01L2933/005 ,  Y10S438/977 ,  H01L2924/00

摘要： Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.

摘要翻译： 这里描述了用于制造，组装和布置电子设备的可打印结构和方法。 本文描述的许多方法对于组装电子器件是有用的，其中一个或多个器件部件被嵌入在嵌入过程中被图案化的聚合物中，其中沟槽用于器件部件之间的电互连。 本文描述的一些方法可用于通过印刷方法组装电子装置，例如通过干式转印接触印刷方法。 本文还描述了GaN发光二极管以及用于制造和布置GaN发光二极管的方法，例如用于显示器或照明系统。

公开(公告)号：US08841766B2

公开(公告)日：2014-09-23

申请号：US12730411

申请日：2010-03-24

申请人： Chien Ling Hwang ,  Yi-Wen Wu ,  Chun-Chieh Wang ,  Chung-Shi Liu

发明人： Chien Ling Hwang ,  Yi-Wen Wu ,  Chun-Chieh Wang ,  Chung-Shi Liu

IPC分类号： H01L23/50 ,  H01L23/00

CPC分类号： H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03901 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1182 ,  H01L2224/11827 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16238 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/00

摘要： Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.

摘要翻译： 提供了用于Cu柱凸点技术的侧壁保护工艺，其中Cu柱凸起的侧壁上的保护结构由非金属材料层，例如电介质材料层，聚合物材料层或聚合物材料层中的至少一个形成 其组合。

公开(公告)号：US20140187103A1

公开(公告)日：2014-07-03

申请号：US13751289

申请日：2013-01-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Ting Chen ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii

IPC分类号： H01R12/00 ,  H01R43/02

CPC分类号： H01L24/16 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/08238 ,  H01L2224/11334 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13184 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16052 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01R43/0235 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

摘要翻译： 这里提出了一种用于形成它的互连和方法，所述方法包括在设置在第一基板的第一表面上的安装焊盘的安装表面上形成互连，所述互连包括导电材料，可选地焊料或金属，所述互连 避免安装垫的侧面。 将模塑料施加到第一基板的第一表面并且在互连件周围模制以覆盖互连件的至少下部，并且第二基板可以安装在互连件上。 互连可以包括设置在第一和第二基板之间的互连材料和设置在第一基板的表面上的模制化合物，以及暴露互连的一部分。 互连材料的侧壁以与垂直于第一衬底的平面成小于约30度的角度接触安装衬垫。

公开(公告)号：US08546925B2

公开(公告)日：2013-10-01

申请号：US13247174

申请日：2011-09-28

申请人： Juan A. Herbsommer ,  Osvaldo J. Lopez ,  Jonathan A. Noquil ,  David Jauregui ,  Mark E. Granahan

发明人： Juan A. Herbsommer ,  Osvaldo J. Lopez ,  Jonathan A. Noquil ,  David Jauregui ,  Mark E. Granahan

IPC分类号： H01L23/02

CPC分类号： H01L24/05 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/072 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2924/01029 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15321 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/014 ,  H01L2924/00

摘要： A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

摘要翻译： 一种封装的电源模块（100），包括具有第一功率场效应晶体管（FET）的芯片（110）和第二芯片（120），其中第二FET导体地并排连接到导电载体（130）上， 所述晶体管具有第一区域（210）的接合焊盘，并且所述载体具有比所述第一区域小的第二区域（230）的接合焊盘。 连接到晶体管接合焊盘的导电凸块（114,115,124,125）和连接到载体接合焊盘的导电凸块（126）具有相等的体积并且是共面的（150），晶体管焊盘上的凸块具有第一高度和 载体垫上的凸起具有大于第一高度的第二高度。

公开(公告)号：US20130187268A1

公开(公告)日：2013-07-25

申请号：US13357379

申请日：2012-01-24

申请人： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

发明人： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/1131 ,  H01L2224/11424 ,  H01L2224/1152 ,  H01L2224/1162 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00014 ,  H01L2924/00

摘要： A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

摘要翻译： 提供一种用于封装半导体管芯的系统和方法。 实施例包括具有第一触点和第二触点的第一封装。 在第一接触件上形成接触后材料，以便调节接触垫之间的接头的高度，导体凸块。 在另一个实施例中，使用导电柱来控制接触垫和外部连接之间的接头的高度。

公开(公告)号：US12100679B2

公开(公告)日：2024-09-24

申请号：US17967472

申请日：2022-10-17

申请人： Dialog Semiconductor (UK) Limited

发明人： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

IPC分类号： H01L23/31 ,  H01L23/00

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L23/3114 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/20641 ,  H01L2924/20646 ,  H01L2924/2075 ,  H01L2924/20752 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/94 ,  H01L2224/11

摘要： A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

公开(公告)号：US20240249950A1

公开(公告)日：2024-07-25

申请号：US18449452

申请日：2023-08-14

申请人： Western Digital Technologies, Inc.

发明人： Yangming Liu ,  Bo Yang ,  Ning Ye

IPC分类号： H01L21/3065 ,  H01L21/82 ,  H01L23/00

CPC分类号： H01L21/3065 ,  H01L21/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2924/20641

摘要： Approaches directed at increasing the production yield of integrated circuits including layers of low-k dielectrics. One example provides a flip-chip assembly including a semiconductor chip attached to a substrate using pillars or bumps. The semiconductor chip has a thickness profile such that the chip is thinner near the corners than in middle portions. The thinner corner portions beneficially alleviate chip-integrity issues related to the stresses generated during the solder reflow operation while the thicker middle portions beneficially alleviate chip-integrity issues related to the stresses generated during the chip or die pick-up operation. Due to the alleviation of both types of chip-integrity issues, the number of instances in which the low-k dielectrics crack during the corresponding assembly operations is significantly reduced, thereby beneficially increasing the manufacturing yield.

公开(公告)号：US20190122976A1

公开(公告)日：2019-04-25

申请号：US16228928

申请日：2018-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Min Liang ,  Jiun Yi Wu

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H01L21/66

CPC分类号： H01L23/49838 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/17132 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/05042 ,  H01L2924/0533 ,  H01L2924/0534 ,  H01L2924/05342 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05994 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0353 ,  H01L2924/014 ,  H01L2924/00014

摘要： A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.