专利检索 cpc:"H01L2224/05664" 第 2 页

11.

发明授权
Package with solder regions aligned to recesses 有权

公开(公告)号：US09947630B2

公开(公告)日：2018-04-17

申请号：US15417942

申请日：2017-01-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Jung Yang , Hsien-Wei Chen , Hsien-Ming Tu , Chang-Pin Huang , Yu-Chia Lai , Tung-Liang Shao

IPC分类号： H01L21/44 , H01L23/48 , H01L23/52 , H01L23/00

CPC分类号： H01L24/02 , H01L21/76802 , H01L23/3171 , H01L23/49811 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/02311 , H01L2224/02351 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/0346 , H01L2224/03464 , H01L2224/0347 , H01L2224/0362 , H01L2224/03622 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05018 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05548 , H01L2224/05555 , H01L2224/05558 , H01L2224/05563 , H01L2224/05569 , H01L2224/05572 , H01L2224/05582 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/1132 , H01L2224/11849 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13147 , H01L2224/73204 , H01L2924/01029 , H01L2924/14 , H01L2924/181 , H01L2924/014 , H01L2924/00

摘要： A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

12.

发明申请
Remapped Packaged Extracted Die 审中-公开

公开(公告)号：US20180047685A1

公开(公告)日：2018-02-15

申请号：US15792312

申请日：2017-10-24

申请人： Erick Merle Spory

发明人： Erick Merle Spory

IPC分类号： H01L23/00 , H01L23/26 , H01L23/498 , H01L23/057

CPC分类号： H01L24/05 , H01L23/057 , H01L23/10 , H01L23/26 , H01L23/49838 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/85 , H01L24/98 , H01L2224/03424 , H01L2224/03464 , H01L2224/04042 , H01L2224/05124 , H01L2224/05147 , H01L2224/05554 , H01L2224/05583 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/73265 , H01L2224/85207 , H01L2924/16152 , H01L2924/19107 , H01L2924/00014

摘要： A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted die includes a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and an interposer, bonded to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads, and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.

13.

发明授权
Semiconductor apparatus, solid state imaging device, imaging apparatus and electronic equipment, and manufacturing method thereof 有权

公开(公告)号：US09881962B2

公开(公告)日：2018-01-30

申请号：US15035839

申请日：2014-11-27

申请人： SONY CORPORATION

发明人： Hidetsugu Otani , Yuuji Kishigami

IPC分类号： H01L27/14 , H01L27/146 , H04N5/225 , H01L23/00

CPC分类号： H01L27/14643 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L27/14618 , H01L27/14636 , H01L27/14683 , H01L27/14689 , H01L2224/02371 , H01L2224/0346 , H01L2224/03602 , H01L2224/0401 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/06182 , H01L2224/131 , H01L2224/16057 , H01L2224/16105 , H01L2224/16227 , H01L2224/94 , H04N5/2253 , H04N5/2254 , H01L2924/014 , H01L2224/03 , H01L2924/00014

摘要： The present technology relates to a semiconductor apparatus, a solid state imaging device, an imaging apparatus and electronic equipment which realize a smaller and thinner size and which enable improvement of optical characteristics, and a manufacturing method thereof. A side electrode 16c is formed on a side face of a substrate on which an imaging device 16 is formed. By this side electrode 16c being connected to an electrode pad 15b on the substrate 15 through a chip wiring 17 formed with solder, the imaging device 16 is electrically connected to the substrate 15. By this means, because it is possible to electrically connect the imaging device 16 to the substrate 15 without using wire bonding, space required for wire bonding is not required, so that it is possible to realize a smaller and thinner apparatus. The present technology can be applied to an imaging apparatus.

14.

发明授权
Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars 有权

公开(公告)号：US09875988B2

公开(公告)日：2018-01-23

申请号：US14927361

申请日：2015-10-29

申请人： Semtech Corporation

发明人： Satyamoorthi Chinnusamy , Weng Hing Tan , Andrew Pan , Kok Khoon Ho

IPC分类号： H01L21/44 , H01L25/065 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/495 , H01L23/498 , H01L25/00 , H01L23/552 , H01L23/29 , H01L23/433 , H01L23/00

CPC分类号： H01L25/065 , H01L21/4825 , H01L21/486 , H01L21/4882 , H01L21/56 , H01L21/561 , H01L21/565 , H01L23/295 , H01L23/3107 , H01L23/3121 , H01L23/3192 , H01L23/367 , H01L23/4334 , H01L23/49541 , H01L23/49827 , H01L23/552 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L25/50 , H01L2224/05008 , H01L2224/05548 , H01L2224/05567 , H01L2224/05569 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/1147 , H01L2224/13005 , H01L2224/13013 , H01L2224/13014 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/16057 , H01L2224/16238 , H01L2224/32245 , H01L2224/73253 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2224/97 , H01L2924/3841 , H01L2224/11 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/01028 , H01L2924/01079 , H01L2924/01046 , H01L2924/2064 , H01L2924/2075 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2224/03 , H01L2224/81

摘要： A semiconductor device has a first semiconductor die disposed over a substrate. A plurality of composite interconnect structures are formed over the semiconductor die. The composite interconnect structures have a non-fusible conductive pillar and a fusible layer formed over the non-fusible conductive pillar. The fusible layer is reflowed to connect the first semiconductor die to a conductive layer of the substrate. The non-fusible conductive pillar does not melt during reflow eliminating a need to form a solder resist over the substrate. An encapsulant is deposited around the first semiconductor die and composite interconnect structures. The encapsulant flows between the active surface of the first semiconductor die and the substrate. A second semiconductor die is disposed over the substrate adjacent to the first semiconductor die. A heat spreader is disposed over the first semiconductor die. A portion of the encapsulant is removed to expose the heat spreader.

15.

发明申请
SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES 审中-公开

公开(公告)号：US20180019219A1

公开(公告)日：2018-01-18

申请号：US15545670

申请日：2015-02-25

申请人： INTEL CORPORATION

发明人： Srinivas V. Pietambaram , Kyu Oh Lee

IPC分类号： H01L23/00 , B23K35/26 , H01L23/498 , C22C13/00 , C22C19/03

CPC分类号： H01L24/05 , B23K35/262 , C22C13/00 , C22C19/03 , H01L23/49811 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05147 , H01L2224/05564 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05664 , H01L2224/0568 , H01L2224/05683 , H01L2224/05684 , H01L2224/13026 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16227 , H01L2224/16238 , H01L2224/81444 , H01L2924/01015 , H01L2924/014 , H01L2924/15311 , H01L2924/00014 , H01L2924/01082 , H01L2924/01083 , H01L2924/01029 , H01L2924/01047

摘要： A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

16.

发明申请
SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20170372996A1

公开(公告)日：2017-12-28

申请号：US15621745

申请日：2017-06-13

申请人： Renesas Electronics Corporation

发明人： Masahiro MATSUMOTO , Akira Yajima , Kazuyoshi Maekawa

IPC分类号： H01L23/498 , H01L23/13 , H01L23/00

CPC分类号： H01L23/49838 , H01L23/13 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/97 , H01L2224/02166 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05554 , H01L2224/05558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00

摘要： A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.

17.

发明申请
SEMICONDUCTOR DEVICE AND METHOD COMPRISING REDISTRIBUTION LAYERS 审中-公开

公开(公告)号：US20170372964A1

公开(公告)日：2017-12-28

申请号：US15695772

申请日：2017-09-05

申请人： DECA Technologies Inc.

发明人： Christopher M. Scanlan , Craig Bishop

IPC分类号： H01L21/78 , H01L21/56 , H01L23/48 , H01L23/31 , H01L21/768 , H01L23/00 , H01L23/498 , H01L23/29

CPC分类号： H01L21/78 , H01L21/561 , H01L21/568 , H01L21/76877 , H01L23/295 , H01L23/3114 , H01L23/3128 , H01L23/48 , H01L23/49827 , H01L23/562 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/92 , H01L24/94 , H01L24/96 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02377 , H01L2224/0239 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05024 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05548 , H01L2224/05568 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/0558 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05687 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/2101 , H01L2224/214 , H01L2224/215 , H01L2224/32225 , H01L2224/73267 , H01L2224/92 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/3511 , Y02P80/30 , H01L2224/11 , H01L2924/01029 , H01L2924/014 , H01L2924/01028 , H01L2924/0105 , H01L2924/00 , H01L2924/01082 , H01L2924/01074 , H01L2924/01023 , H01L2924/01013 , H01L2924/01079 , H01L2924/01047 , H01L2224/0231 , H01L2924/00014 , H01L2924/04941 , H01L21/304 , H01L23/3164 , H01L2224/03 , H01L2224/19 , H01L2924/01322

摘要： A method of making a semiconductor package can include placing a single layer dielectric film on a temporary carrier substrate. A plurality of semiconductor die can be placed directly on the first surface of the single layer dielectric film. The single layer dielectric film can be cured to lock the plurality of semiconductor die in place on the single layer dielectric film. The plurality of semiconductor die can be encapsulated while directly on the single layer dielectric film with an encapsulant. The single layer dielectric film can be patterned utilizing a mask-less patterning technique to form a via hole after removing the temporary carrier substrate. A conductive layer can be formed directly on, substantially parallel to, and extending across, the second surface of the patterned single layer dielectric film, within the vial hole, and over the plurality of semiconductor die.

18.

发明授权
Semiconductor device having multiple contact clips 有权

公开(公告)号：US09837380B2

公开(公告)日：2017-12-05

申请号：US14165720

申请日：2014-01-28

申请人： Infineon Technologies Austria AG

发明人： Tian San Tan , Theng Chao Long

IPC分类号： H01L23/00 , H01L25/065 , H01L21/56 , H01L23/31 , H01L25/00 , H01R4/00 , H01L25/07 , H01L23/433 , H01L23/495

CPC分类号： H01L25/0655 , H01L21/56 , H01L23/3107 , H01L23/3121 , H01L23/4334 , H01L23/49513 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/38 , H01L24/40 , H01L24/48 , H01L24/70 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/89 , H01L24/97 , H01L25/072 , H01L25/50 , H01L2224/04026 , H01L2224/05554 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32227 , H01L2224/32245 , H01L2224/33181 , H01L2224/37011 , H01L2224/37013 , H01L2224/37026 , H01L2224/3719 , H01L2224/40227 , H01L2224/40245 , H01L2224/40499 , H01L2224/48227 , H01L2224/48245 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83143 , H01L2224/83447 , H01L2224/83801 , H01L2224/83815 , H01L2224/83825 , H01L2224/8384 , H01L2224/83855 , H01L2224/84143 , H01L2224/84447 , H01L2224/84801 , H01L2224/84815 , H01L2224/84825 , H01L2224/8484 , H01L2224/8485 , H01L2224/84855 , H01L2224/97 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/1425 , H01L2924/14252 , H01L2924/14253 , H01L2924/181 , H01R4/00 , H01L2924/00 , H01L2924/0105 , H01L2924/01049 , H01L2924/01014 , H01L2924/014 , H01L2924/00012 , H01L2224/45099 , H01L2224/83 , H01L2224/84

摘要： A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.

19.

发明申请
Surface Conditioning And Material Modification In A Semiconductor Device 审中-公开

公开(公告)号：US20170345780A1

公开(公告)日：2017-11-30

申请号：US15162867

申请日：2016-05-24

申请人： Texas Instruments Incorporated

发明人： Murlidhar Bashyam , Richard Allen Faust

IPC分类号： H01L23/00

CPC分类号： H01L24/03 , H01L21/02074 , H01L24/05 , H01L2224/03466 , H01L2224/03614 , H01L2224/03616 , H01L2224/0362 , H01L2224/0381 , H01L2224/03848 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05155 , H01L2224/05186 , H01L2224/05562 , H01L2224/05571 , H01L2224/05664 , H01L2224/05666 , H01L2224/05686 , H01L2924/00012 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953

摘要： A plasma-based ashing process for surface conditioning and material modification to improve bond pad metallurgical properties as well as semiconductor device performance. Residue materials generated in a removal process at a process layer having recessed features with Ni—Pd surfaces are ashed in a plasma reactor to reduce defect count and improve surface conditioning associated with bond pads of the semiconductor device.