公开(公告)号：US20240071990A1

公开(公告)日：2024-02-29

申请号：US17896030

申请日：2022-08-25

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/81 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81481 ,  H01L2224/81483 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/3841

摘要： A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.

公开(公告)号：US11749534B1

公开(公告)日：2023-09-05

申请号：US17957683

申请日：2022-09-30

申请人： Deca Technologies USA, Inc.

发明人： Robin Davis ,  Paul R. Hoffman ,  Clifford Sandstrom ,  Timothy L. Olson

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L21/4839 ,  H01L21/561 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81481 ,  H01L2224/81484

摘要： A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.

公开(公告)号：US20190013271A1

公开(公告)日：2019-01-10

申请号：US16129577

申请日：2018-09-12

申请人： INTEL CORPORATION

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/482 ,  H01L25/18 ,  H01L23/532

CPC分类号： H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20170196133A1

公开(公告)日：2017-07-06

申请号：US15314914

申请日：2015-05-22

申请人： Sharp Kabushiki Kaisha

发明人： Katsuhiro YAMAGUCHI ,  Nobuhiro NAKATA ,  Yukinori MASUDA ,  Tomoki TAKAHARA

IPC分类号： H05K13/04 ,  H05K3/00 ,  H01L23/00 ,  H05K1/11

CPC分类号： H05K13/0469 ,  G02F1/13454 ,  H01L24/03 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/2949 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/7525 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75312 ,  H01L2224/75744 ,  H01L2224/75981 ,  H01L2224/75985 ,  H01L2224/81048 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81234 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81903 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/83234 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K1/111 ,  H05K3/0055 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

摘要： An array substrate includes a driver, a glass substrate having a driver mounting section where the driver is mounted, an anisotropic conductive material that is interposed between the driver and driver mounting section so as to electrically connect both and that at least includes a binder made of a thermosetting resin and conductive particles in the binder, and a heat supply part provided on at least the driver mounting section of the glass substrate for supplying heat to the anisotropic conductive material.

公开(公告)号：US09640485B2

公开(公告)日：2017-05-02

申请号：US14836906

申请日：2015-08-26

申请人： INTEL CORPORATION

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/482 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18 ,  H05K3/34

CPC分类号： H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US09508680B1

公开(公告)日：2016-11-29

申请号：US14741757

申请日：2015-06-17

申请人： GLOBALFOUNDRIES INC.

发明人： Stephen P. Ayotte ,  Glen E. Richard ,  Timothy M. Sullivan

IPC分类号： H01L23/00 ,  C09K5/06 ,  H01L21/56

CPC分类号： H01L24/98 ,  C09K5/06 ,  H01L21/56 ,  H01L21/563 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/069 ,  H01L2924/05381 ,  H01L2924/0549 ,  H01L2924/054 ,  H01L2924/01028 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/01048 ,  H01L2924/0537 ,  H01L2924/01025 ,  H01L2924/0532 ,  H01L2924/01012 ,  H01L2924/05442

摘要： Underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate. The underfill material may a plurality of particles dispersed in a bulk matrix. The material constituting the particles may be capable of generating heat energy when exposed to a time-varying magnetic field. The bulk matrix of the underfill material between the chip and a substrate may be heated with heat energy transferred from the particles. While heated, the underfill material is removed. The heating of the underfill material may also be used to heat solder bumps connecting the chip with the substrate so that the solder bumps are liquefied.

摘要翻译： 用于从芯片下面去除底部填充材料的底部填充材料和方法相对于从衬底移除芯片。 底部填充材料可以分散在块状基质中的多个颗粒。 构成颗粒的材料可以在暴露于时变磁场时能够产生热能。 芯片和衬底之间的底部填充材料的主体矩阵可以用从颗粒转移的热能来加热。 加热时，去除底部填充材料。 底部填充材料的加热也可以用于加热将芯片与衬底连接的焊料凸块，使得焊料凸块液化。

公开(公告)号：US09275967B2

公开(公告)日：2016-03-01

申请号：US14148482

申请日：2014-01-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Min Liang ,  Jiun-Yi Wu

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/66

CPC分类号： H01L23/49838 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/17132 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/05042 ,  H01L2924/0533 ,  H01L2924/0534 ,  H01L2924/05342 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05994 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0353 ,  H01L2924/014 ,  H01L2924/00014

摘要： A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

摘要翻译： 提供了一个管芯和一个衬底。 芯片包括至少一个集成电路芯片，并且该基板包括至少部分延伸穿过其中的导电柱的第一和第二子集。 导电柱的第一子集中的每一个包括从衬底的表面突出的突出隆起焊盘，并且导电柱的第二子集各自部分地形成凹陷在衬底的表面内的迹线。 裸片经由多个导电凸块耦合到基板，每个导电凸块在突起凸块焊盘和模具中的一个之间延伸。

公开(公告)号：US20150294928A1

公开(公告)日：2015-10-15

申请号：US14669169

申请日：2015-03-26

申请人： ROHM CO., LTD.

发明人： Kenji FUJII ,  Yasumasa KASUYA ,  Mamoru YAMAGAMI ,  Naoki KINOSHITA ,  Motoharu HAGA

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L23/49527 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/4822 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49572 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/33 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11825 ,  H01L2224/13008 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13624 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/16014 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/17107 ,  H01L2224/29008 ,  H01L2224/29082 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/75981 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/8183 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83466 ,  H01L2224/8383 ,  H01L2224/92225 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/07025 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/01028 ,  H01L2924/0665

摘要： A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

摘要翻译： 半导体器件具有设置有功能表面的半导体元件，功能电路形成在其上，并且背面面向与功能表面相反的方向，同时还具有支撑半导体元件并与半导体元件电连接的引线 以及覆盖半导体元件和引线的至少一部分的树脂封装。 半导体元件具有形成在功能面上的功能面侧电极，其具有在功能面朝向的方向突出的功能面侧凸起部。 功能面侧电极的功能面侧隆起部通过固态接合而与引线接合。

公开(公告)号：US20150102395A1

公开(公告)日：2015-04-16

申请号：US14511801

申请日：2014-10-10

申请人： Jae-Hwa Park ,  Kwang-Jin Moon ,  Byung-Lyul Park

发明人： Jae-Hwa Park ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC分类号： H01L27/108 ,  H01L23/64 ,  H01L49/02 ,  H01L23/48 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L23/481 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

摘要： An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate.

摘要翻译： 集成电路器件包括其中具有第一和第二半导体区域的半导体衬底，第一半导体区域中的栅极沟槽和栅极沟槽中的栅电极。 栅电极在半导体衬底的表面下方具有上表面。 半导体阱区域设置在第二半导体区域中。 电容器沟槽在半导体阱区域中延伸，并且上电容器电极在电容器沟槽中延伸。 提供电互连（例如，导电插头），其在它们之间的界面处电连接到上电容器电极。 该界面在半导体衬底的表面下方具有上表面。

公开(公告)号：US20140353827A1

公开(公告)日：2014-12-04

申请号：US13903828

申请日：2013-05-28

申请人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/00

CPC分类号： H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。