公开(公告)号：US4906823A

公开(公告)日：1990-03-06

申请号：US202027

申请日：1988-06-03

Applicant: Tadao Kushima ,  Tasao Soga ,  Kazuji Yamada ,  Mitugu Shirai

Inventor： Tadao Kushima ,  Tasao Soga ,  Kazuji Yamada ,  Mitugu Shirai

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/49827 ,  H05K3/3478 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19042 ,  H05K2201/09827 ,  H05K2201/10734 ,  H05K2201/2081 ,  H05K2203/0113 ,  H05K2203/0143 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  Y10T29/49218

Abstract: The invention relates to a solder carrier comprising a sheet of self-support type, made of a material which does not react to a solder when it is melted, a plurality of small through holes, and solder filling the through holes, each of the small through holes having an end, the area of which is larger than that of the other end. By using this solder carrier, a semiconductor device can be flip-chip-connected to a carrier substrate through a bump method, and solder balls can be formed for connecting the carrier substrate to a multilayer circuit board. The through holes of the solder carrier, each of which holes is to be filled with solder, is formed by etching, and the solder is inserted in the holes under pressure by a roll or the like.

Abstract translation: 本发明涉及一种焊料载体，它包括一种自支撑型材料，它由熔化时不与焊料反应的材料制成，多个小通孔和填充通孔的焊料，每个小型 具有端部的通孔，其面积大于另一端的面积。 通过使用该焊料载体，可以通过凸块法将半导体器件倒装芯片连接到载体基板，并且可以形成用于将载体基板连接到多层电路板的焊球。 通过蚀刻形成每个要填充有焊料的孔的焊料载体的通孔，并且通过辊等将焊料插入孔中。

公开(公告)号：US4825284A

公开(公告)日：1989-04-25

申请号：US940485

申请日：1986-12-10

Applicant: Tasao Soga ,  Marahiro Goda ,  Fumio Nakano ,  Tadao Kushima ,  Nobuyuki Ushifusa ,  Fumiyuki Kobayashi ,  Mamoru Sawahata

Inventor： Tasao Soga ,  Marahiro Goda ,  Fumio Nakano ,  Tadao Kushima ,  Nobuyuki Ushifusa ,  Fumiyuki Kobayashi ,  Mamoru Sawahata

IPC: H01L23/52 ,  H01L21/56 ,  H01L21/60 ,  H01L23/433 ,  H01L23/473 ,  H01L23/498 ,  H01L23/538 ,  H01L25/11 ,  H01L39/02

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/4332 ,  H01L23/49827 ,  H01L23/5385 ,  H01L25/112 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/351

Abstract: A semiconductor resin package structure formed according to the flip-chip connection method and permitting to cool the rear surface of semiconductor chips, comprising semiconductor chip and carrier substrate which is soldered on one surface thereof to electrodes of the semiconductor chip according to the flip-chip connection method, the gap between the semiconductor chip and the carrier substrate being filled with resin having a thermal expansion coefficient, which is approximately equal to that of used solder, the electrodes of the semiconductor chip being electrically connected with terminals on the other surface of the carrier substrate through the soldered portions and a through-hole conductor disposed on the carrier substrate, the thermal expansion coefficient of the carrier substrate being approximately equal to that of a multi-layer substrate, with which the substrate is connected by soldering with the terminals.

Abstract translation: 根据倒装芯片连接方法形成的半导体树脂封装结构，并且允许冷却半导体芯片的背面，该半导体芯片包括半导体芯片和载体基板，该半导体芯片和载体基板在其一个表面上焊接到根据倒装芯片的半导体芯片的电极 连接方法中，半导体芯片和载体基板之间的间隙充满了热膨胀系数的树脂，其热膨胀系数近似等于使用的焊料的热膨胀系数，所述半导体芯片的电极与所述半导体芯片的另一表面上的端子电连接 通过焊接部分的载体衬底和布置在载体衬底上的通孔导体，载体衬底的热膨胀系数近似等于多层衬底的热膨胀系数，衬底通过与端子焊接而与其连接。

公开(公告)号：US4503597A

公开(公告)日：1985-03-12

申请号：US464379

申请日：1983-02-07

Applicant: Tadao Kushima ,  Masahiro Gooda ,  Tasao Soga ,  Toshitaka Yamamoto

Inventor： Tadao Kushima ,  Masahiro Gooda ,  Tasao Soga ,  Toshitaka Yamamoto

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12043

Abstract: A method of forming a number of discrete solder layers on a semiconductor wafer of a large area. A number of regions which are easy to be wetted with solder are formed on one of the major surfaces of the wafer. A solder foil is positioned on the one major surface and a plate-like jig including a plate and projections formed on one surface thereof is disposed on the solder foil with the projections facing the latter. By heating the stacked assembly at a sufficiently high temperature for the solder foil to be molten, a number of the discrete solder layers having a uniform thickness are formed on the semiconductor wafer.

Abstract translation: 在大面积的半导体晶片上形成多个分立焊料层的方法。 在晶片的一个主表面上形成许多容易被焊料润湿的区域。 焊锡箔位于一个主表面上，并且包括在其一个表面上形成的板和突起的板状夹具设置在焊料箔上，其中突起面向其上。 通过在足够高的温度下加热堆叠的组件以使焊料箔熔融，在半导体晶片上形成多个具有均匀厚度的分立焊料层。

公开(公告)号：US4562637A

公开(公告)日：1986-01-07

申请号：US622584

申请日：1984-06-20

Applicant: Tadao Kushima ,  Tasao Soga ,  Takaya Suzuki

Inventor： Tadao Kushima ,  Tasao Soga ,  Takaya Suzuki

IPC: H01L31/042 ,  H01L31/05 ,  H05K3/36 ,  H01L31/18

CPC classification number: H01L31/1876 ,  H01L31/0512 ,  H05K3/363 ,  Y02E10/50 ,  Y02P70/521 ,  Y10T29/49169 ,  Y10T29/49179 ,  Y10T29/49181

Abstract: A method of manufacturing a solar battery by serially connecting a plurality of solar battery elements arranged spaced from each other. A pair of flexible films are used to sandwich the arrangement of the solar battery elements, and each of the flexible films has a plurality of conductive members formed thereon at positions respectively corresponding to the solar battery elements. However, each conductive member has one end portion extended beyond the surface of the corresponding solar battery element in the direction of the alignment of the solar battery elements. Thus, when the pair of flexible films are disposed to sandwich the solar battery elements, the extended end portion of the conductive member on the side of the light receiving surface of one solar battery element is positioned in the space between adjacent solar battery elements opposite the end portion of the conductive member on the side of the back surface of the next solar battery element. By welding both end portions of the conductive members by, for example, a laser beam, the adjacent solar battery elements are successively connected in series.

Abstract translation: 通过串联连接彼此间隔布置的多个太阳能电池元件来制造太阳能电池的方法。 使用一对柔性膜来夹持太阳能电池元件的布置，并且每个柔性膜在分别对应于太阳能电池元件的位置处形成有多个导电构件。 然而，每个导电构件具有在太阳能电池元件的对准方向上延伸超过相应的太阳能电池元件的表面的一个端部。 因此，当一对柔性膜被设置成夹持太阳能电池元件时，导电构件的一个太阳能电池元件的光接收表面侧的延伸端部位于相邻的太阳能电池元件之间的空间中 导电构件的下一个太阳能电池元件的背面侧的端部。 通过例如通过激光束焊接导电部件的两端部，相邻的太阳能电池元件依次连续地连接。

公开(公告)号：US4970577A

公开(公告)日：1990-11-13

申请号：US337145

申请日：1989-04-12

Applicant: Satoru Ogihara ,  Shunichi Numata ,  Kunio Miyazaki ,  Takashi Yokoyama ,  Ken Takahashi ,  Tasao Soga ,  Kazuji Yamada ,  Hiroichi Shinohara ,  Hideo Suzuki

Inventor： Satoru Ogihara ,  Shunichi Numata ,  Kunio Miyazaki ,  Takashi Yokoyama ,  Ken Takahashi ,  Tasao Soga ,  Kazuji Yamada ,  Hiroichi Shinohara ,  Hideo Suzuki

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/64 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01L23/642 ,  H01L23/49827 ,  H01L23/49833 ,  H05K1/141 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/0271 ,  H05K1/0306 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K3/3426 ,  H05K3/368

Abstract: A semiconductor chip module includes semiconductor chips each of which has contacts on its entire front face. A multi-layered organic circuit board having a small dielectric constant is provided for mounting the semiconductor chips. Intermediate ceramic substrates having the same thermal expansion coefficient as that of the semiconductor chip, are also provided. Each such intermediate ceramic substrate has contacts on its front and back faces corresponding to those of the semiconductor chip. These contacts are electrically connected directly in a one-to-one relationship. The contacts on the semiconductor chip and the corresponding ones on the front face of the intermediate ceramic substrates are connected by solder. The contacts on the back face of the intermediate ceramic substrate and the corresponding contacts on the front face of the multi-layered ceramic circuit board are connected by respective conductive pins having a predetermined flexibility and rigidity through a predetermined gap therebetween. With this arrangement, the relative displacement due to a thermal expansion difference between the intermediate ceramic substrate and the multi-layered organic circuit board is permitted without causing substantial stress thereon.

公开(公告)号：US4908695A

公开(公告)日：1990-03-13

申请号：US178650

申请日：1988-04-07

Applicant: Atsushi Morihara ,  Yoshio Naganuma ,  Shuntaro Koyama ,  Kazuji Yamada ,  Tasao Soga ,  Hideo Arakawa ,  Shunsuke Nogita ,  Yukio Hishinuma

Inventor： Atsushi Morihara ,  Yoshio Naganuma ,  Shuntaro Koyama ,  Kazuji Yamada ,  Tasao Soga ,  Hideo Arakawa ,  Shunsuke Nogita ,  Yukio Hishinuma

IPC: H01L23/36 ,  H01L23/433 ,  H01L23/473 ,  H05K7/20

CPC classification number: H01L23/4338 ,  H01L2224/16

Abstract: A heat conducting member is placed in the space between a semiconductor chip which generates heat and a heat transfer block which is cooled by a coolant, and the heat conducting member conducts heat from the semiconductor chip to the heat transfer block. The heat conducting member has a slanted surface which is inclined with respect to a surface to be cooled of the corresponding semiconductor chip. Even when the semiconductor chip is displaced or inclined with respect to the heat transfer block, the whole of the cooling surface of the semiconductor chip can be kept in contact with the corresponding heat conducting member.

公开(公告)号：US07259465B2

公开(公告)日：2007-08-21

申请号：US10104826

申请日：2002-03-22

Applicant: Tasao Soga ,  Hanae Shimokawa ,  Tetsuya Nakatsuka ,  Kazuma Miura ,  Mikio Negishi ,  Hirokazu Nakajima ,  Tsuneo Endoh

Inventor： Tasao Soga ,  Hanae Shimokawa ,  Tetsuya Nakatsuka ,  Kazuma Miura ,  Mikio Negishi ,  Hirokazu Nakajima ,  Tsuneo Endoh

IPC: H01L29/40

CPC classification number: H01L24/13 ,  B32B15/01 ,  C22C5/02 ,  C22C9/02 ,  C22C11/06 ,  C22C13/00 ,  H01L21/50 ,  H01L21/56 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/4924 ,  H01L23/49513 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81024 ,  H01L2224/81054 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81409 ,  H01L2224/81815 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/141 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/045 ,  H05K2201/09572 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01031 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/83205

Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Abstract translation: 形成在半导体器件和衬底之间的接合部包括Cu等的金属球，Sn和金属球的化合物以及金属球通过化合物结合在一起。

公开(公告)号：US07013564B2

公开(公告)日：2006-03-21

申请号：US09971566

申请日：2001-10-09

Applicant: Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

Inventor： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

IPC: H01R43/00 ,  H05K13/00

CPC classification number: H05K1/181 ,  B23K1/0016 ,  B23K35/004 ,  B23K35/007 ,  B23K35/262 ,  B23K2101/40 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/532 ,  H01L24/29 ,  H01L2224/83101 ,  H01L2924/01322 ,  H01L2924/15747 ,  H05K3/3426 ,  H05K3/3463 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T428/12708 ,  Y10T428/12715 ,  H01L2924/00

Abstract: A method of producing an electronic device by connecting a lead of a semiconductor device with an electrode of a circuit board to form a bonded structure. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

Abstract translation: 一种通过将半导体器件的引线与电路板的电极连接以形成接合结构来制造电子器件的方法。 在接合结构中，通过Sn-Bi合金层将无铅Sn-Ag-Bi合金焊料施加到电极。 Sn-Bi合金优选含有1〜20重量％的Bi，以获得良好的焊料润湿性。 为了获得本发明中具有较高可靠性的理想的接合特性，在Sn-Bi合金层下方设置有铜层，从而获得足够的接合强度。

公开(公告)号：US06486411B2

公开(公告)日：2002-11-26

申请号：US09811445

申请日：2001-03-20

Applicant: Kazuma Miura ,  Hanae Shimokawa ,  Koji Serizawa ,  Tasao Soga ,  Tetsuya Nakatsuka

Inventor： Kazuma Miura ,  Hanae Shimokawa ,  Koji Serizawa ,  Tasao Soga ,  Tetsuya Nakatsuka

IPC: H05K103

CPC classification number: H05K3/3463 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T428/12715 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module solder bonding of high reliability in which the heat resisting properties of the circuit substrate and electronic parts are taken into consideration. In order to achieve this, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.

Abstract translation: 考虑到电路基板和电子部件的耐热性能的高可靠性的半导体模块焊接。 为了实现这一点，提供了各自具有作为外部焊盘的焊料凸块的半导体器件，以及通过焊膏将每个半导体器件的外部焊盘接合的电路基板，每个焊料凸块由第一引线 焊锡膏由熔点低于第一无铅焊料的第二无铅焊料制成。

公开(公告)号：US08125090B2

公开(公告)日：2012-02-28

申请号：US12843934

申请日：2010-07-27

Applicant: Tasao Soga ,  Daisuke Kawase ,  Kazuhiro Suzuki ,  Eiichi Morisaki ,  Katsuaki Saito ,  Hanae Shimokawa

Inventor： Tasao Soga ,  Daisuke Kawase ,  Kazuhiro Suzuki ,  Eiichi Morisaki ,  Katsuaki Saito ,  Hanae Shimokawa

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/24 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/0603 ,  H01L2224/26145 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48491 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/3651 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3463 ,  H05K2201/10977 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2924/3512

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract translation: 由于环境问题，使用无铅焊料变得至关重要。 电源模块通过焊接大面积的基板形成。 已知在Sn-3Ag-0.5Cu中，相对于基板的翘曲变形很大而难以蠕变变形，相对于温度循环试验，寿命显着缩短，现有的模块结构在 难以确保高可靠性。 因此，本发明的目的是选择可以在低应变率下预期寿命增加的组合物。 在Sn焊料中，通过将In掺杂3〜7％，Ag增加2〜4.5％，发现在低应变速率下延迟裂纹扩展的效果，作为代表性组合物在高温下稳定，Sn-3Ag- 选择0.5Cu-5In。 此外，为了提高可靠性，示出了用树脂部分地涂覆焊料端部的方法。