公开(公告)号：US09847309B2

公开(公告)日：2017-12-19

申请号：US13476410

申请日：2012-05-21

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L21/28 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L27/146

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14618 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.

公开(公告)号：US09824975B2

公开(公告)日：2017-11-21

申请号：US14612075

申请日：2015-02-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/538 ,  H01L25/07 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant.

公开(公告)号：US09818734B2

公开(公告)日：2017-11-14

申请号：US14624136

申请日：2015-02-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L21/66 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/82

Abstract: A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

公开(公告)号：US20170297903A1

公开(公告)日：2017-10-19

申请号：US15362199

申请日：2016-11-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L25/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00904 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

公开(公告)号：US20170278765A1

公开(公告)日：2017-09-28

申请号：US15618343

申请日：2017-06-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Thomas J. Strothmann ,  Seung Wook Yoon ,  Yaojian Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/73267 ,  H01L2924/13091 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.

公开(公告)号：US09768102B2

公开(公告)日：2017-09-19

申请号：US13425768

申请日：2012-03-21

Applicant: Dong Ju Jeon ,  Koo Hong Lee ,  Sung Soo Kim

Inventor： Dong Ju Jeon ,  Koo Hong Lee ,  Sung Soo Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.

公开(公告)号：US20170236802A1

公开(公告)日：2017-08-17

申请号：US15582418

申请日：2017-04-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Ming-Che Hsieh ,  Chien Chen Lee ,  Baw-Ching Perng

IPC: H01L23/00

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/0001 ,  H01L2924/01007 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/207 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

公开(公告)号：US09728415B2

公开(公告)日：2017-08-08

申请号：US14134907

申请日：2013-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Vinoth Kanna Chockanathan ,  Xing Zhao ,  Duk Ju Na ,  Chang Bum Yong

IPC: H01L23/52 ,  H01L21/306 ,  H01L21/56 ,  H01L21/78 ,  H01L21/304 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/31

CPC classification number: H01L21/30625 ,  H01L21/304 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.

公开(公告)号：US09693455B1

公开(公告)日：2017-06-27

申请号：US14227346

申请日：2014-03-27

Applicant: Seong Won Park ,  Hun Teak Lee ,  WoonJae Beak ,  MinJung Kim ,  ChangHwan Kim ,  ByungHyun Kwak ,  GwangTae Kim ,  HeeSoo Lee

Inventor： Seong Won Park ,  Hun Teak Lee ,  WoonJae Beak ,  MinJung Kim ,  ChangHwan Kim ,  ByungHyun Kwak ,  GwangTae Kim ,  HeeSoo Lee

IPC: H05K1/11 ,  H05K3/36 ,  H05K3/40 ,  H05K1/09 ,  H05K1/18 ,  H05K1/14 ,  H05K3/32 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/09 ,  H05K1/113 ,  H05K1/14 ,  H05K1/18 ,  H05K1/186 ,  H05K3/32 ,  H05K3/36 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/04 ,  H05K2203/061 ,  H05K2203/0733

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a copper film; a first metal layer directly on the copper film; an insulation layer directly on and over the first metal layer, the insulation layer having a via hole through the insulation layer; a conductive via within the via hole and directly on the first metal layer; a second metal layer directly on the conductive via and the insulation layer; a copper post directly on the copper film; a solder pad over the copper post; and an interposer coupled to the copper post and the solder pad.

公开(公告)号：US09685495B2

公开(公告)日：2017-06-20

申请号：US13423265

申请日：2012-03-18

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H05K7/00 ,  H01L49/02 ,  H01L23/14 ,  H01L23/498 ,  H01L23/64 ,  H01L27/01 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L27/016 ,  H01L28/24 ,  H01L28/60 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73207 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.