公开(公告)号：US12092861B2

公开(公告)日：2024-09-17

申请号：US16929799

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  H04B10/80 ,  H04Q11/00

CPC classification number: G02B6/12004 ,  G02B6/30 ,  G02B6/4206 ,  G02B6/4214 ,  G02B6/4274 ,  G02B6/428 ,  H04B10/801 ,  H04B10/807 ,  H04Q11/0005 ,  H04Q2011/0035

Abstract: A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

公开(公告)号：US12087732B2

公开(公告)日：2024-09-10

申请号：US18338013

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Yung-Chi Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/683 ,  H01L21/82 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/6836 ,  H01L21/82 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582

Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

公开(公告)号：US12080615B2

公开(公告)日：2024-09-03

申请号：US18068010

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2224/94 ,  H01L2224/214 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2224/19 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US12057410B2

公开(公告)日：2024-08-06

申请号：US18359684

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

公开(公告)号：US12051616B2

公开(公告)日：2024-07-30

申请号：US18298780

申请日：2023-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/10 ,  H01L25/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/768 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/105 ,  H01L25/115 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/13099 ,  H01L2224/14135 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2203/1316

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

公开(公告)号：US20240250020A1

公开(公告)日：2024-07-25

申请号：US18602665

申请日：2024-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/07 ,  H01L25/075 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/38 ,  H01L33/62

CPC classification number: H01L23/5226 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/11 ,  H01L24/89 ,  H01L25/072 ,  H01L25/0753 ,  H01L33/0093 ,  H01L33/38 ,  H01L33/62 ,  H01L21/3212 ,  H01L24/81 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/08225 ,  H01L2224/08501 ,  H01L2224/80006 ,  H01L2224/80815 ,  H01L2224/80895 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

公开(公告)号：US20240222242A1

公开(公告)日：2024-07-04

申请号：US18609836

申请日：2024-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US12015023B2

公开(公告)日：2024-06-18

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US12015008B2

公开(公告)日：2024-06-18

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US12009335B2

公开(公告)日：2024-06-11

申请号：US17833034

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L25/105 ,  H01L24/03 ,  H01L24/11 ,  H01L24/20 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13019 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/27462 ,  H01L2224/29026 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81121 ,  H01L2224/81125 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/8191 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/0347 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81895 ,  H01L2924/00014 ,  H01L2224/81121 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/00014 ,  H01L2924/1206 ,  H01L2924/00014 ,  H01L2924/1207 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.