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公开(公告)号:US09871064B1
公开(公告)日:2018-01-16
申请号:US15283271
申请日:2016-09-30
发明人: Quan Jing , Jin Xu , Minjie Chen , Yu Ren , Yukun Lv , Jun Zhu , Xusheng Zhang
IPC分类号: H01L21/00 , H01L27/146 , H01L21/3213 , H01L21/04 , H01L21/027 , H01L21/311 , H01L21/762 , H01L21/31
CPC分类号: H01L27/1461 , H01L21/02057 , H01L21/0274 , H01L21/0475 , H01L21/31 , H01L21/31116 , H01L21/31138 , H01L21/3213 , H01L21/76229 , H01L27/14687
摘要: The invention disclosed a method for forming shallow trenches of the dual active regions. Firstly, forming an etch stop layer on a semiconductor substrate; secondly, using a first accurate photomask to expose and develop the semiconductor substrate, until the etch stop layer has been exposed on the top of the first shallow trench regions and the second shallow trench regions; thirdly, etching the etch stop layer entirely in the exposed regions; fourthly, using a second photomask to expose and develop the first shallow trench regions which require a deeper etch depth of the trench than that of the second shallow trench regions; fifthly, etching and forming preliminary entirely depth in the first shallow trench regions, and then removing the second photomask; at last, taking the etch stop layer as a mask, and simultaneously etching the first shallow trench regions and the second shallow trench regions to form the first hallow trenches and the second shallow trenches having different depths. The invention has realized a low-cost photomask application and an optimization of the etching process by optimizing the photomask design.
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公开(公告)号:US09842902B1
公开(公告)日:2017-12-12
申请号:US15672549
申请日:2017-08-09
发明人: Fujio Masuoka , Hiroki Nakamura
IPC分类号: H01L29/423 , H01L29/66 , H01L21/308 , H01L21/3105 , H01L21/311 , H01L21/321 , H01L21/3213 , H01L29/78 , H01L21/02 , H01L27/088 , H01L21/8234 , H01L21/28 , H01L29/08 , H01L29/10 , H01L29/40 , H01L21/285
CPC分类号: H01L29/42356 , H01L21/02532 , H01L21/28088 , H01L21/28114 , H01L21/28525 , H01L21/308 , H01L21/31051 , H01L21/31105 , H01L21/31144 , H01L21/32115 , H01L21/3213 , H01L21/823487 , H01L27/088 , H01L29/0847 , H01L29/1037 , H01L29/401 , H01L29/42364 , H01L29/66545 , H01L29/66666 , H01L29/7827
摘要: An SGT is produced by forming a first insulating film around a fin-shaped semiconductor layer, forming a pillar-shaped semiconductor layer in an upper portion of the fin-shaped layer, forming a second insulating film, a polysilicon gate electrode covering the second insulating film, and a polysilicon gate line, forming a diffusion layer in an upper portion of the fin-shaped layer and a lower portion of the pillar-shaped layer, forming a metal-semiconductor compound in an upper portion of the diffusion layer in the fin-shaped layer, depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and gate line, depositing a first metal, forming a metal gate electrode and a metal gate line, and forming a third metal sidewall on an upper side wall of the pillar-shaped layer. The third metal sidewall is connected to an upper surface of the pillar-shaped layer.
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公开(公告)号:US20170352548A1
公开(公告)日:2017-12-07
申请号:US15686922
申请日:2017-08-25
发明人: Wen-Kuei Liu , Teng-Chun Tsai , Kuo-Yin Lin , Shen-Nan Lee , Yu-Wei Chou , Kuo-Cheng Lien , Chang-Sheng Lin , Chih-Chang Hung , Yung-Cheng Lu
IPC分类号: H01L21/3105 , H01L21/84 , H01L21/28 , H01L21/3213 , H01L21/027 , H01L21/311 , H01L29/66 , H01L21/8238
CPC分类号: H01L21/31055 , H01L21/0273 , H01L21/0274 , H01L21/28008 , H01L21/31058 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/3213 , H01L21/32139 , H01L21/823821 , H01L21/845 , H01L29/66545
摘要: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.
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公开(公告)号:US09778561B2
公开(公告)日:2017-10-03
申请号:US14610038
申请日:2015-01-30
发明人: Jeffrey Marks , George Andrew Antonelli , Richard A. Gottscho , Dennis M. Hausmann , Adrien LaVoie , Thomas Joseph Knisley , Sirish K. Reddy , Bhadri N. Varadarajan , Artur Kolics
IPC分类号: B05D3/06 , G03F1/76 , C23C18/14 , C23C18/16 , C23C18/18 , H01L21/033 , H01L21/3213 , G03F7/004 , G03F7/16
CPC分类号: G03F1/76 , C23C18/14 , C23C18/1612 , C23C18/165 , C23C18/182 , G03F7/0043 , G03F7/16 , G03F7/167 , H01L21/0332 , H01L21/0337 , H01L21/3213
摘要: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
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公开(公告)号:US20170278879A1
公开(公告)日:2017-09-28
申请号:US15506904
申请日:2015-08-27
IPC分类号: H01L27/12 , H01L29/786 , G02F1/1368
CPC分类号: H01L27/1296 , G02F1/1368 , H01L21/28 , H01L21/3213 , H01L21/768 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L29/78669 , H01L29/78693
摘要: The present invention includes: a multilayer film forming step of forming a multilayer film constituted by a plurality of metal films layered together; after the multilayer film forming step, a resist forming step of forming a resist film having patterned openings on the multilayer film; after the resist forming step, a dry etching step of dry etching the multilayer film to remove at least one metal film located at the top of the multilayer film and exposed by the openings; after the dry etching step, a wet etching step of wet etching the multilayer film to remove at least the metal films exposed by the openings.
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公开(公告)号:US20170256588A1
公开(公告)日:2017-09-07
申请号:US15074338
申请日:2016-03-18
发明人: Natsuki FUKUDA , Mutsumi OKAJIMA , Atsushi OGA , Toshiharu TANAKA , Takeshi YAMAGUCHI , Takeshi TAKAGI , Masanori KOMURA
IPC分类号: H01L27/24 , H01L21/3213 , H01L21/311 , H01L21/768
CPC分类号: H01L27/2481 , H01L21/311 , H01L21/3213 , H01L21/76805 , H01L21/76816 , H01L21/8221 , H01L23/5226 , H01L23/5329 , H01L27/0688 , H01L27/101 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/7926
摘要: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
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公开(公告)号:US20170162718A1
公开(公告)日:2017-06-08
申请号:US15439997
申请日:2017-02-23
发明人: Shunpei YAMAZAKI , Yasutaka NAKAZAWA , Masami JINTYOU , Junichi KOEZUKA , Kenichi OKAZAKI , Takuya HIROHASHI , Shunsuke ADACHI
IPC分类号: H01L29/786 , H01L27/12 , H01L29/66
CPC分类号: H01L29/78696 , H01L21/32051 , H01L21/3213 , H01L21/473 , H01L21/4757 , H01L27/1225 , H01L27/3262 , H01L29/66969 , H01L29/78618 , H01L29/7869
摘要: A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing Ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment.
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公开(公告)号:US20170162541A1
公开(公告)日:2017-06-08
申请号:US15437193
申请日:2017-02-20
发明人: Yu-Feng Chen , Kai-Chiang Wu , Chun-Lin Lu , Hung-Jui Ko
IPC分类号: H01L23/00 , H01L21/78 , H01L23/544
CPC分类号: H01L21/3205 , H01L21/283 , H01L21/3213 , H01L21/34 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/76898 , H01L21/78 , H01L23/10 , H01L23/147 , H01L23/16 , H01L23/28 , H01L23/31 , H01L23/3157 , H01L23/4334 , H01L23/481 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/544 , H01L23/562 , H01L23/564 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2021/6024 , H01L2223/5446 , H01L2224/02235 , H01L2224/02255 , H01L2224/0226 , H01L2224/03462 , H01L2224/03464 , H01L2224/03622 , H01L2224/0401 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05572 , H01L2224/06181 , H01L2224/11318 , H01L2224/13026 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/1703 , H01L2224/17181 , H01L2224/17505 , H01L2224/17517 , H01L2224/32145 , H01L2224/73204 , H01L2224/81139 , H01L2224/92124 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06568 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/06 , H01L2924/0665 , H01L2924/07025 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/18161 , H01L2924/2064 , H01L2924/3511 , H01L2224/81 , H01L2924/00
摘要: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.
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公开(公告)号:US09646874B1
公开(公告)日:2017-05-09
申请号:US13959136
申请日:2013-08-05
申请人: Sandia Corporation
IPC分类号: H01L21/00 , H01L21/764 , H01L29/06 , H01L21/762
CPC分类号: H01L21/823481 , B81C1/00 , H01L21/02178 , H01L21/02532 , H01L21/02592 , H01L21/30604 , H01L21/31111 , H01L21/3213 , H01L21/762 , H01L21/764 , H01L21/84 , H01L23/34 , H01L27/12 , H01L29/0649 , H03H3/02 , H03H2009/02181
摘要: Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.
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公开(公告)号:US09583601B2
公开(公告)日:2017-02-28
申请号:US15002826
申请日:2016-01-21
发明人: Shunpei Yamazaki , Yasutaka Nakazawa , Masami Jintyou , Junichi Koezuka , Kenichi Okazaki , Takuya Hirohashi , Shunsuke Adachi
IPC分类号: H01L29/786 , H01L29/66 , H01L21/3205 , H01L21/3213 , H01L21/473 , H01L21/4757
CPC分类号: H01L29/78696 , H01L21/32051 , H01L21/3213 , H01L21/473 , H01L21/4757 , H01L27/1225 , H01L27/3262 , H01L29/66969 , H01L29/78618 , H01L29/7869
摘要: A method for manufacturing a semiconductor device including a transistor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer to form a stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing Ti is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes; and regions in the oxide layer in contact with the source and drain electrodes are heat treated so as to have a low resistivity.
摘要翻译: 提供一种制造包括具有稳定的电气特性或高可靠性的晶体管的半导体器件的方法。 在栅电极上形成栅极绝缘膜; 在栅绝缘膜上形成氧化物半导体层; 在氧化物半导体层上形成氧化物层,形成包含氧化物半导体层和氧化物层的层叠氧化膜; 堆叠层氧化膜被加工成预定的形状; 在堆叠层氧化膜上形成含有Ti的导电膜; 蚀刻导电膜以形成源极和漏极; 并且与源极和漏极接触的氧化物层中的区域被热处理以具有低电阻率。
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