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202 条记录 (耗时 0.025 秒)

    Memory circuit
    31.
    发明授权
    Memory circuit 有权
    存储电路

    公开(公告)号：US08787083B2

    公开(公告)日：2014-07-22

    申请号：US13365999

    申请日：2012-02-03

    申请人： Masashi Fujita

    发明人： Masashi Fujita

    IPC分类号： G11C11/34 ,  G11C14/00 ,  G11C7/00 ,  G11C5/00 ,  G11C5/06 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C11/40 ,  G11C5/005 ,  G11C5/06 ,  G11C7/00 ,  G11C7/20 ,  G11C11/34 ,  G11C14/00 ,  G11C14/0009 ,  G11C14/0054 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/792

    摘要： While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.

    摘要翻译： 在电源供应停止的情况下，可以将保持在易失性存储部中的数据信号保持在非易失性存储部。 在非易失性存储器部分中，具有极低截止电流的晶体管允许数据信号长时间保持在电容器中。 因此，即使在停止供电时，非易失性存储部也能够保持逻辑状态。 当再次开始供电时，在电源供应停止时保持在电容器中的数据信号被设定为通过接通复位电路而不发生故障的电位。

    Memory circuit, signal processing circuit, and electronic device
    32.
    发明授权
    Memory circuit, signal processing circuit, and electronic device 有权
    存储电路，信号处理电路和电子设备

    公开(公告)号：US08681533B2

    公开(公告)日：2014-03-25

    申请号：US13453135

    申请日：2012-04-23

    申请人： Masashi Fujita

    发明人： Masashi Fujita

    IPC分类号： G11C11/24

    CPC分类号： H01L27/00 ,  G11C7/1006 ,  G11C11/401 ,  G11C14/0009 ,  H01L27/1225

    摘要： A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided.

    摘要翻译： 提供了使用具有新颖结构的非易失性存储器电路的信号处理电路。 非易失性存储器电路使用包括氧化物半导体的晶体管和连接到晶体管的源极和漏极之一的电容器来形成。 高电位电位被预先写入存储电路，并且在保存数据具有高电位电位的情况下保持该状态，而在存储电路中写入低电位电位的情况下， 要保存的数据具有低级潜力。 因此，可以提供具有改善的写入速度的信号处理电路。

    SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS
    33.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS 有权
    具有数据传输和接收电路的半导体集成电路

    公开(公告)号：US20120223769A1

    公开(公告)日：2012-09-06

    申请号：US13470972

    申请日：2012-05-14

    申请人： Masayasu KOMYO ,  Yoichi IIzuka

    发明人： Masayasu KOMYO ,  Yoichi IIzuka

    IPC分类号： H04B1/10

    CPC分类号： H03K19/00361 ,  G11C7/1006 ,  G11C14/0009 ,  H03K19/0005 ,  H03K19/00315

    摘要： Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.

    摘要翻译： 提供了根据本发明的示例性方面的半导体集成电路，包括数据发送电路和数据接收电路，其接收从数据发送电路发送的数据。 数据发送电路包括输出数据或将输出设置为高阻抗状态的数据输出电路和向数据输出电路输出控制信号的控制电路，使得数据输出电路在数据发送时输出数据 在数据发送电路在发送数据之后进一步发送另一数据时，数据输出电路在先前的数据传输之后的预定时段期间，数据输出电路继续输出上一次数据传输中的数据。

    Asynchronous/synchronous interface
    34.
    发明授权
    Asynchronous/synchronous interface 有权
    异步/同步接口

    公开(公告)号：US08248868B2

    公开(公告)日：2012-08-21

    申请号：US13078563

    申请日：2011-04-01

    申请人： Dean K. Nobunaga ,  June Lee ,  Chih Liang Chen

    发明人： Dean K. Nobunaga ,  June Lee ,  Chih Liang Chen

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1072 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C14/0009 ,  G11C16/10 ,  Y02D10/14

    摘要： The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

    摘要翻译： 本公开包括用于操作存储器件的方法和电路。 用于操作存储器件的一个方法实施例包括通过至少部分地响应于第一接口触点上的写入使能信号向存储器件写入数据来控制通过异步模式的存储器接口的数据传输，以及从存储器件读取数据 至少部分地响应于第二接口触点上的读使能信号。 该方法还包括通过至少部分地响应于第一接口触点上的时钟信号传送数据，并且在不在异步模式下使用的接口触点上提供双向数据选通信号，来以同步模式控制数据传输。

    SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING THE SAME
    35.
    发明申请
    SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING THE SAME 有权
    信号处理电路及其驱动方法

    公开(公告)号：US20120051117A1

    公开(公告)日：2012-03-01

    申请号：US13215302

    申请日：2011-08-23

    申请人： Shunpei Yamazaki ,  Jun Koyama

    发明人： Shunpei Yamazaki ,  Jun Koyama

    IPC分类号： G11C11/24

    CPC分类号： G11C14/0054 ,  G11C14/00 ,  G11C14/0009 ,  H01L27/0629

    摘要： An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage element includes two logic elements (referred to as a first phase-inversion element and a second phase-inversion element) which invert a phase of an input signal and output the signal, a first selection transistor, and a second selection transistor. In the storage element, two pairs each having a transistor in which a channel is formed in an oxide semiconductor layer and a capacitor (a pair of a first transistor and a first capacitor, and a pair of a second transistor and a second capacitor) are provided. The storage element is used in a storage device such as a register or a cache memory included in a signal processing circuit.

    摘要翻译： 本发明的目的是提供一种信号处理电路，其可以在没有复杂的制造工艺的情况下制造并且抑制功耗。 存储元件包括反转输入信号的相位并输出信号的两个逻辑元件（称为第一相位反转元件和第二相位反转元件），第一选择晶体管和第二选择晶体管。 在存储元件中，每个具有在氧化物半导体层中形成沟道的晶体管和电容器（一对第一晶体管和第一电容器，以及一对第二晶体管和第二电容器）的两对是 提供。 存储元件用于包括在信号处理电路中的寄存器或高速缓冲存储器等存储装置。