公开(公告)号：US10049998B2

公开(公告)日：2018-08-14

申请号：US15221370

申请日：2016-07-27

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H05K3/34 ,  H05K1/11 ,  H05K1/14 ,  B23K3/06 ,  B23K35/02 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L21/02 ,  B23K1/00 ,  B23K101/40

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

公开(公告)号：US10043779B2

公开(公告)日：2018-08-07

申请号：US15353577

申请日：2016-11-16

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L21/288 ,  H01L25/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L21/48 ,  H01L21/54 ,  H01L23/18 ,  H01L23/538 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/54 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/81005 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15322 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

公开(公告)号：US09947641B2

公开(公告)日：2018-04-17

申请号：US15217084

申请日：2016-07-22

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Wael Zohni ,  Rizza Lee Saga Cizek ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/34 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/498 ,  H01L25/00 ,  H01L21/683 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15312 ,  H01L2924/15321 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

公开(公告)号：US09871019B2

公开(公告)日：2018-01-16

申请号：US15209034

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh

IPC: H01L25/065 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49541 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/18

Abstract: A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

公开(公告)号：US09837330B2

公开(公告)日：2017-12-05

申请号：US15422887

申请日：2017-02-02

Applicant: Invensas Corporation

Inventor： Rajesh Katkar

IPC: H01L21/4763 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/3107 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/10 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83005 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.

公开(公告)号：US09824974B2

公开(公告)日：2017-11-21

申请号：US15364534

申请日：2016-11-30

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Hong Shen ,  Arkalgud R. Sitaram ,  Liang Wang ,  Akash Agrawal ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

公开(公告)号：US09812406B2

公开(公告)日：2017-11-07

申请号：US15280175

申请日：2016-09-29

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao

IPC: H01L23/12 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/053 ,  H01L23/29 ,  H01L23/14 ,  H01L23/15 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/053 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

公开(公告)号：US09793198B2

公开(公告)日：2017-10-17

申请号：US14275519

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/498 ,  B23K35/22 ,  B23K35/02 ,  B32B15/01 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  B23K1/00 ,  B23K101/40

CPC classification number: H01L23/49811 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/0266 ,  B23K35/22 ,  B23K2101/40 ,  B32B15/01 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/03001 ,  H01L2224/03009 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/03334 ,  H01L2224/0348 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05294 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/2401 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/75253 ,  H01L2224/81 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82105 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

Abstract: A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

公开(公告)号：US20170250140A1

公开(公告)日：2017-08-31

申请号：US15592973

申请日：2017-05-11

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5387 ,  H05K1/0203 ,  H05K1/0326 ,  H05K2201/062 ,  H05K2201/10378

Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.

公开(公告)号：US20170179081A1

公开(公告)日：2017-06-22

申请号：US15358380

申请日：2016-11-22

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Tu Tam Vu ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/495

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49051 ,  H01L2224/4909 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.