Patent search cpc:"H05K2201/0379" Page 2

11.

发明申请
RISERS INCLUDING A PLURALITY OF HIGH ASPECT RATIO ELECTRICAL CONDUITS AND SYSTEMS AND METHODS OF MANUFACTURE AND USE THEROF 审中-公开
Title translation: 包括多个高比例电气连接和系统的升高及其制造和使用方法

公开(公告)号：US20130069680A1

公开(公告)日：2013-03-21

申请号：US13610076

申请日：2012-09-11

Applicant: Koby L. Duckworth , Eric Hill , Mike Jolley , Kurt Schultz , Jody Curtis

Inventor： Koby L. Duckworth , Eric Hill , Mike Jolley , Kurt Schultz , Jody Curtis

IPC: G01R1/073 , H05K3/10 , H05K1/11

CPC classification number: G01R1/07378 , G01R3/00 , H05K1/11 , H05K3/4046 , H05K2201/0379 , H05K2201/10378

Abstract: Risers including a plurality of high aspect ratio electrical conduits, as well as systems and methods of manufacture and/or use of the risers and/or the high aspect ratio electrical conduits. The systems and methods may include incorporation of the plurality of high aspect ratio electrical conduits within a substantially planar body that may include and/or be formed from a solid dielectric material. The plurality of electrical conduits may be configured to conduct a plurality of electric currents between a first surface of the body and a second, substantially opposed, surface of the body. The surfaces may include a plurality of contact pads configured to provide a robust and/or corrosion-resistant surface and/or to improve electrical contact between the riser and another device. The risers also may include a layered structure, wherein the layers are sequentially formed to increase a thickness of the riser and/or the aspect ratio of the electrical conduits.

Abstract translation: 包括多个高纵横比电导管的立管以及制造和/或使用立管和/或高纵横比电导管的系统和方法。系统和方法可以包括将多个高纵横比的电导管并入可包括和/或由固体电介质材料形成的基本平坦的体内。多个电导管可以被配置为在主体的第一表面和主体的第二，基本相对的表面之间传导多个电流。表面可以包括多个接触垫，其被配置为提供坚固的和/或耐腐蚀的表面和/或改善上升管和另一个装置之间的电接触。立管还可以包括层状结构，其中顺序地形成这些层以增加提升管的厚度和/或电导管的纵横比。

12.

发明授权
Adhesive for bonding circuit members, circuit board and process for its production 有权

公开(公告)号：US08273457B2

公开(公告)日：2012-09-25

申请号：US13166570

申请日：2011-06-22

Applicant: Itsuo Watanabe , Kenzo Takemura , Akira Nagai , Kazuhiro Isaka , Osamu Watanabe , Kazuyoshi Kojima

Inventor： Itsuo Watanabe , Kenzo Takemura , Akira Nagai , Kazuhiro Isaka , Osamu Watanabe , Kazuyoshi Kojima

IPC: B32B27/38

CPC classification number: H01L24/83 , C09J9/02 , H01L23/49883 , H01L24/29 , H01L24/90 , H01L2224/16225 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/45144 , H01L2224/73204 , H01L2224/83101 , H01L2224/8319 , H01L2224/838 , H01L2224/83851 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H05K1/0271 , H05K3/323 , H05K2201/0133 , H05K2201/0209 , H05K2201/0379 , H05K2203/1189 , Y10T29/49117 , Y10T156/10 , Y10T156/109 , Y10T428/24942 , Y10T428/24959 , Y10T428/2852 , Y10T428/31511 , Y10T428/31515 , Y10T428/31855 , H01L2924/00

Abstract: An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.

13.

发明授权
Methods for manufacturing device mounting board and circuit substrate 失效
Title translation: 制造装置安装板和电路基板的方法

公开(公告)号：US08183090B2

公开(公告)日：2012-05-22

申请号：US12856168

申请日：2010-08-13

Applicant: Mayumi Nakasato , Hideki Mizuhara , Takaya Kusabe , Sadamichi Takakusaki

Inventor： Mayumi Nakasato , Hideki Mizuhara , Takaya Kusabe , Sadamichi Takakusaki

IPC: H05K3/10

CPC classification number: H05K3/305 , H01L21/4846 , H01L21/4857 , H01L23/49833 , H01L2224/16225 , H01L2224/16227 , H05K1/0262 , H05K1/056 , H05K1/141 , H05K1/183 , H05K3/107 , H05K3/4614 , H05K3/4694 , H05K3/4697 , H05K2201/0195 , H05K2201/0355 , H05K2201/0379 , H05K2201/09472 , H05K2201/09972 , H05K2201/10378 , H05K2201/10545 , H05K2201/10734 , H05K2201/10977 , H05K2203/0278 , H05K2203/1189 , Y02P70/613 , Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部上的第二导电层（包括导电部）和形成在基底的顶部的第三导电层的基地。这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

14.

发明授权
Circuit board and method for manufacturing thereof 有权
Title translation: 电路板及其制造方法

公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim

Inventor： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim

IPC: H05K1/03

CPC classification number: H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

15.

发明申请
ADHESIVE FOR BONDING CIRCUIT MEMBERS, CIRCUIT BOARD AND PROCESS FOR ITS PRODUCTION 有权

公开(公告)号：US20110247873A1

公开(公告)日：2011-10-13

申请号：US13166570

申请日：2011-06-22

Applicant: Itsuo WATANABE , Kenzo Takemura , Akira Nagai , Kazuhiro Isaka , Osamu Watanabe , Kazuyoshi Kojima

Inventor： Itsuo WATANABE , Kenzo Takemura , Akira Nagai , Kazuhiro Isaka , Osamu Watanabe , Kazuyoshi Kojima

IPC: H05K1/11 , H05K13/04 , B32B37/14 , B32B37/10 , B32B37/12

CPC classification number: H01L24/83 , C09J9/02 , H01L23/49883 , H01L24/29 , H01L24/90 , H01L2224/16225 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/45144 , H01L2224/73204 , H01L2224/83101 , H01L2224/8319 , H01L2224/838 , H01L2224/83851 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H05K1/0271 , H05K3/323 , H05K2201/0133 , H05K2201/0209 , H05K2201/0379 , H05K2203/1189 , Y10T29/49117 , Y10T156/10 , Y10T156/109 , Y10T428/24942 , Y10T428/24959 , Y10T428/2852 , Y10T428/31511 , Y10T428/31515 , Y10T428/31855 , H01L2924/00

Abstract: An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.

16.

发明申请
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
Title translation: 半导体器件及其制造方法

公开(公告)号：US20110084383A1

公开(公告)日：2011-04-14

申请号：US12903403

申请日：2010-10-13

Applicant: Daisuke MIZUTANI

Inventor： Daisuke MIZUTANI

IPC: H01L23/48 , H01L21/50

CPC classification number: H05K1/147 , H01L21/76898 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H05K1/0218 , H05K1/141 , H05K3/222 , H05K3/3436 , H05K3/363 , H05K2201/0379 , H05K2201/0715 , H05K2201/09063 , H05K2201/092 , H05K2201/10666 , H05K2201/10734 , H05K2203/167 , Y02P70/613 , H01L2924/00

Abstract: A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.

Abstract translation: 半导体器件包括：第一电路基体部件，其包括形成有多个第一电极的表面;第二电路基体部件，设置在第一电路基体的上方，并具有分别形成在第一电极上方的第一通孔和第二通孔; 设置在第二电路基体上方的封装，以及设置在第一通孔内的多个第一凸起和第二通孔，以将第一电极连接到半导体封装。

17.

发明授权
Device having a bonding structure for two elements 有权
Title translation: 具有用于两个元件的结合结构的装置

公开(公告)号：US07737552B2

公开(公告)日：2010-06-15

申请号：US12126766

申请日：2008-05-23

Applicant: Eric Beyne

Inventor： Eric Beyne

IPC: H01L23/34 , H01L21/00 , H01R12/16

CPC classification number: H01L23/3128 , H01L21/561 , H01L21/563 , H01L23/5225 , H01L23/5227 , H01L23/552 , H01L23/66 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2223/6677 , H01L2224/11005 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/1191 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2224/9211 , H01L2224/92125 , H01L2224/92222 , H01L2224/94 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/1433 , H01L2924/15331 , H01L2924/1627 , H01L2924/181 , H01L2924/3025 , H05K3/3436 , H05K2201/0379 , H05K2201/10977 , Y02P70/613 , H01L2924/3512 , H01L2924/00 , H01L2924/014 , H01L2224/11 , H01L2224/81 , H01L2924/0665 , H01L2224/45099 , H01L2224/83 , H01L2924/00012

Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

Abstract translation: 描述用于结合元件的装置和方法。在第一元件的主表面上产生第一焊球。在第二元件的主表面上产生第二焊球。在第一焊球和第二焊球之间提供接触。第一和第二元件通过施加回流作用而结合，由此焊球熔化并形成接合的焊球结构。在接合之前，第一焊球侧向嵌入在第一非导电材料层中，并且第二焊球侧向嵌入第二非导电材料层中，使得第一焊球的上部和第二焊球的上部不被非导电材料覆盖。在接合之前，在嵌入的第一或第二焊球的一个或两个上施加第三焊料体积。

18.

发明申请
PRINTED CIRCUIT BOARD ASSEMBLY 有权
Title translation: 印刷电路板组装

公开(公告)号：US20100000766A1

公开(公告)日：2010-01-07

申请号：US12492001

申请日：2009-06-25

Applicant: Emmanuel Loiselet , Phil Wills

Inventor： Emmanuel Loiselet , Phil Wills

IPC: H05K1/02 , H05K3/36

CPC classification number: H01L23/433 , H01L23/367 , H01L23/473 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H05K1/0203 , H05K3/0061 , H05K2201/0379 , H05K2201/09054 , H05K2201/10734 , H05K2203/167 , Y10T29/49126 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: An assembly comprising a first printed circuit board, PCB, with a ball grid array, BGA, on its underside, a second PCB facing the first PCB and having at least one through-hole between its top and bottom surfaces, its top surface printed with a circuit pattern bonded to the BGA, a heat sink layer facing the bottom surface of the second PCB and having at least one thermally-conductive pin projecting normally into the through-hole or a respective one of the through-holes in the second PCB, and, for each pin, a thermally-conductive stud of the same cross-section as the pin, bonded to the BGA and disposed within the through-hole between the pin and the first PCB in thermal contact with the pin.

Abstract translation: 一种组件，其包括第一印刷电路板，具有球栅阵列的PCB，BGA，其下侧，面对第一PCB的第二PCB，并且在其顶表面和底表面之间具有至少一个通孔，其顶表面印有结合到BGA的电路图案，面向第二PCB的底表面的散热层，并且具有至少一个通常插入通孔中的导热针或第二PCB中的相应一个通孔，并且对于每个销，具有与销相同的横截面的导热柱，其与所述BGA结合并且设置在所述销和所述第一PCB之间的与所述销热接触的通孔中。

19.

发明申请
Microelectronic Package Having Second Level Interconnects Including Stud Bumps and Method of Forming Same 审中-公开
Title translation: 具有二级互连的微电子封装，包括螺柱冲击和形成方法

公开(公告)号：US20090057866A1

公开(公告)日：2009-03-05

申请号：US11845427

申请日：2007-08-27

Applicant: Linda L. W. Chow

Inventor： Linda L. W. Chow

IPC: H01L23/52 , H01L21/00

CPC classification number: H01L23/49816 , H01L23/055 , H01L23/10 , H01L2224/1134 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01025 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/16152 , H01L2924/3511 , H05K3/328 , H05K3/3436 , H05K2201/0367 , H05K2201/0379 , H05K2201/09136 , H05K2201/094 , Y02P70/613 , H01L2924/00012 , H01L2924/00

Abstract: A microelectronic package and a method of forming the package. The microelectronic package includes a first level package including: a package substrate having a die side and a carrier side a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects etectrically coupling the die to the package substrate. The microelectronic package further includes: a carrier having a substrate side, the first level package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the first level package to the carrier, each of the second level interconnects including a stud bump made substantially of Au.

Abstract translation: 微电子封装和形成封装的方法。微电子封装包括：第一级封装，包括：封装基板，其具有裸片侧和载体侧，微芯片在其芯片侧安装在封装基板上; 以及将管芯耦合到封装衬底的一级互连阵列。微电子封装还包括：具有基板侧的载体，第一级封装在基板侧安装在载体上; 以及将所述第一电平封装电耦合到所述载体的第二电平互连阵列，所述第二电平互连中的每一个包括基本由Au形成的柱形凸块。