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公开(公告)号:US20180301436A1
公开(公告)日:2018-10-18
申请号:US16008531
申请日:2018-06-14
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L25/065 , H01L49/02 , B81B7/00 , H01L25/00 , H01L25/16 , H01L23/00 , H01L23/538 , H01L23/522 , H01L23/498 , H01L23/48 , H01L23/42 , H01L23/367 , H01L21/48
CPC classification number: H01L25/0657 , B81B7/0074 , H01L21/4853 , H01L23/3675 , H01L23/42 , H01L23/481 , H01L23/49811 , H01L23/522 , H01L23/5383 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/0239 , H01L2224/0332 , H01L2224/0333 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03614 , H01L2224/0391 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05184 , H01L2224/05547 , H01L2224/05565 , H01L2224/05568 , H01L2224/05569 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05684 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13565 , H01L2224/13616 , H01L2224/1403 , H01L2224/14131 , H01L2224/14132 , H01L2224/14134 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/17181 , H01L2224/24147 , H01L2224/24227 , H01L2224/244 , H01L2224/32145 , H01L2224/3303 , H01L2224/33181 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48149 , H01L2224/4903 , H01L2224/73201 , H01L2224/73253 , H01L2224/73265 , H01L2224/81192 , H01L2224/81193 , H01L2224/81825 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/16251 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/3841 , H01L2924/00 , H01L2924/01029 , H01L2924/014 , H01L2924/00012 , H01L2924/01028 , H01L2224/05 , H01L2224/13 , H01L2224/81 , H01L2224/45099
Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.
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公开(公告)号:US10103094B2
公开(公告)日:2018-10-16
申请号:US15626687
申请日:2017-06-19
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Pezhman Monadgemi , Terrence Caskey , Fatima Lina Ayatollahi , Belgacem Haba , Charles G. Woychik , Michael Newman
IPC: H05K1/00 , H01L23/498 , H01L23/48 , H01L23/36 , H01L23/373 , H01L21/768 , H01L23/367
Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
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公开(公告)号:US10049998B2
公开(公告)日:2018-08-14
申请号:US15221370
申请日:2016-07-27
Applicant: Invensas Corporation
Inventor: Rajesh Katkar , Cyprian Emeka Uzoh
IPC: H01L23/00 , H05K3/34 , H05K1/11 , H05K1/14 , B23K3/06 , B23K35/02 , H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L25/065 , H01L25/10 , H01L25/00 , H01L21/02 , B23K1/00 , B23K101/40
Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.
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公开(公告)号:US20180218998A1
公开(公告)日:2018-08-02
申请号:US15937149
申请日:2018-03-27
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L25/065 , H01L25/00
CPC classification number: H01L24/81 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/80 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/03009 , H01L2224/0401 , H01L2224/05571 , H01L2224/05572 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05616 , H01L2224/05639 , H01L2224/05644 , H01L2224/05684 , H01L2224/11009 , H01L2224/11464 , H01L2224/13018 , H01L2224/13019 , H01L2224/13084 , H01L2224/13562 , H01L2224/13564 , H01L2224/13655 , H01L2224/13684 , H01L2224/13686 , H01L2224/13805 , H01L2224/13809 , H01L2224/13811 , H01L2224/13844 , H01L2224/13847 , H01L2224/13855 , H01L2224/16148 , H01L2224/16238 , H01L2224/16265 , H01L2224/16268 , H01L2224/16501 , H01L2224/2919 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/81026 , H01L2224/81065 , H01L2224/81099 , H01L2224/81193 , H01L2224/8181 , H01L2224/83026 , H01L2224/83815 , H01L2225/06513 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , H01L2924/19043 , H01L2924/19104 , H01L2924/3841 , H01L2924/013 , H01L2924/00014 , H01L2924/00012
Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
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公开(公告)号:US10015881B2
公开(公告)日:2018-07-03
申请号:US14573461
申请日:2014-12-17
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Craig Mitchell , Belgacem Haba , Ilyas Mohammed
CPC classification number: H05K1/0271 , H01L23/49827 , H01L2924/0002 , H01R12/714 , H05K1/114 , H05K1/115 , H05K3/42 , H05K2201/09645 , H05K2201/10378 , H05K2203/0242 , H05K2203/025 , Y10T29/49165 , H01L2924/00
Abstract: A method is disclosed for making an interconnection component. The steps include forming a mask layer covering a first opening in a sheet-like element that has first and second opposed surfaces; forming a plurality of mask openings in the mask layer, wherein the first opening and a portion of the first surface are partly aligned with each mask opening; and forming electrical conductors on spaced apart portions of the first surface and on spaced apart portions of the interior surface within the first opening which are exposed by the mask openings. The element may consist essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. Each conductor may extend along an axial direction of the first opening and the first conductors may be fully separated from one another within the first opening.
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公开(公告)号:US09871019B2
公开(公告)日:2018-01-16
申请号:US15209034
申请日:2016-07-13
Applicant: Invensas Corporation
Inventor: Ashok S. Prabhu , Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh
IPC: H01L25/065 , H01L23/495 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L23/3107 , H01L23/3157 , H01L23/49541 , H01L24/19 , H01L24/96 , H01L2224/02371 , H01L2224/04105 , H01L2224/18
Abstract: A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.
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公开(公告)号:US09853000B2
公开(公告)日:2017-12-26
申请号:US15181861
申请日:2016-06-14
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh
CPC classification number: H01L23/562 , H01L21/32051 , H01L21/78 , H01L22/12 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2224/0345 , H01L2224/05124 , H01L2224/05181 , H01L2924/12042 , H01L2924/00
Abstract: To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.
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公开(公告)号:US09824974B2
公开(公告)日:2017-11-21
申请号:US15364534
申请日:2016-11-30
Applicant: Invensas Corporation
Inventor: Guilian Gao , Cyprian Emeka Uzoh , Charles G. Woychik , Hong Shen , Arkalgud R. Sitaram , Liang Wang , Akash Agrawal , Rajesh Katkar
IPC: H01L23/48 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/00 , H01L23/31 , H01L21/48 , H01L21/683 , H01L23/498 , H01L23/14 , H01L23/15
CPC classification number: H01L23/5385 , H01L21/486 , H01L21/6835 , H01L23/147 , H01L23/15 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/08225 , H01L2224/16225 , H01L2224/16227 , H01L2224/32105 , H01L2224/32106 , H01L2224/32225 , H01L2224/48091 , H01L2224/48101 , H01L2224/48105 , H01L2224/48137 , H01L2224/48227 , H01L2224/49097 , H01L2224/73204 , H01L2924/00014 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.
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公开(公告)号:US09793198B2
公开(公告)日:2017-10-17
申请号:US14275519
申请日:2014-05-12
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/498 , B23K35/22 , B23K35/02 , B32B15/01 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/00 , B23K1/00 , B23K101/40
CPC classification number: H01L23/49811 , B23K1/0016 , B23K35/0244 , B23K35/0266 , B23K35/22 , B23K2101/40 , B32B15/01 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3135 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/73 , H01L24/742 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/98 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/03 , H01L2224/03001 , H01L2224/03009 , H01L2224/03318 , H01L2224/0332 , H01L2224/0333 , H01L2224/03334 , H01L2224/0348 , H01L2224/03848 , H01L2224/03849 , H01L2224/039 , H01L2224/03901 , H01L2224/0391 , H01L2224/04105 , H01L2224/05022 , H01L2224/051 , H01L2224/05294 , H01L2224/05547 , H01L2224/05567 , H01L2224/05573 , H01L2224/05582 , H01L2224/056 , H01L2224/05794 , H01L2224/05839 , H01L2224/05844 , H01L2224/05847 , H01L2224/05855 , H01L2224/0603 , H01L2224/06102 , H01L2224/10145 , H01L2224/11001 , H01L2224/11005 , H01L2224/11009 , H01L2224/111 , H01L2224/11318 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/11848 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/1191 , H01L2224/13005 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/1319 , H01L2224/13294 , H01L2224/133 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13561 , H01L2224/13562 , H01L2224/13565 , H01L2224/136 , H01L2224/13609 , H01L2224/13611 , H01L2224/1403 , H01L2224/16058 , H01L2224/16059 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/1701 , H01L2224/1703 , H01L2224/17181 , H01L2224/17505 , H01L2224/2101 , H01L2224/211 , H01L2224/2401 , H01L2224/2402 , H01L2224/24137 , H01L2224/24146 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73267 , H01L2224/75253 , H01L2224/81 , H01L2224/81138 , H01L2224/81141 , H01L2224/81193 , H01L2224/81203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81224 , H01L2224/81815 , H01L2224/82005 , H01L2224/82101 , H01L2224/82102 , H01L2224/82105 , H01L2224/83 , H01L2224/8385 , H01L2224/9211 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2924/07025 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/3512 , H01L2924/381 , H01L2924/3841
Abstract: A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.
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公开(公告)号:US20170250140A1
公开(公告)日:2017-08-31
申请号:US15592973
申请日:2017-05-11
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/00 , H05K1/02 , H05K1/03 , H01L23/498 , H01L21/48
CPC classification number: H01L23/562 , H01L21/4846 , H01L21/4857 , H01L21/486 , H01L23/15 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/49866 , H01L23/49894 , H01L23/5384 , H01L23/5387 , H05K1/0203 , H05K1/0326 , H05K2201/062 , H05K2201/10378
Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.
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