公开(公告)号：US09449944B2

公开(公告)日：2016-09-20

申请号：US14422615

申请日：2013-12-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Susumu Sawada ,  Seiichi Nakatani ,  Yoshihisa Yamashita ,  Koji Kawakita

IPC: H01L31/0203 ,  H01L25/065 ,  H01L33/54 ,  H01L33/62 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/288 ,  H01L23/538 ,  H01L25/16 ,  H01L25/00 ,  H01L33/50 ,  H01L21/48 ,  H01L25/075 ,  H01L23/433 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L21/288 ,  H01L21/4878 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/433 ,  H01L23/5386 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0753 ,  H01L25/167 ,  H01L25/50 ,  H01L33/507 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2933/0041 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/32245 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11

Abstract: There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.

Abstract translation: 提供了一种制造电子部件封装的方法，其中第一电子部件和第二电子部件被放置在载体上，并且在载体上形成密封树脂层，随后将载体剥离以除去， 从而提供封装前体，其中嵌入第一和第二电子部件，使得第一和第二电子部件中的至少一个的电极在密封树脂层的表面露出。 在放置第一和第二电子部件时，第一和第二电子部件被定位成使得它们的高度水平彼此不同。 在移除载体之后，形成金属镀层，使得金属镀层与第一和第二电子部件中的至少一个的电极的暴露表面接触。

公开(公告)号：US09362987B2

公开(公告)日：2016-06-07

申请号：US14812242

申请日：2015-07-29

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Fred T. Brauchler ,  Randall C. Gray

IPC: H01L27/08 ,  H04B5/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/495 ,  H01L29/739 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31

CPC classification number: H04B5/0081 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/5227 ,  H01L23/564 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/7393 ,  H01L29/7395 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/1206 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H04B5/0031 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.

Abstract translation: 感应通信设备的实施例包括第一和第二IC芯片和电感耦合衬底。 第一IC芯片具有第一线圈。 电感耦合衬底具有第二线圈和第一信号通信接口（例如，第三线圈或接触件）。 第二IC芯片具有第二信号通信接口（例如，第四线圈或触点）。 第一IC芯片和感应耦合衬底被布置成使得第一和第二线圈跨越第一IC芯片和感应耦合衬底之间的间隙对准。 绝缘元件位于第一和第二线圈之间的间隙内，以使第一IC芯片和感应耦合衬底电隔离。 在操作期间，通过线圈之间的感应耦合和通过信号通信接口进行通信，在第一和第二IC芯片之间传送信号。

公开(公告)号：US09177885B2

公开(公告)日：2015-11-03

申请号：US12518262

申请日：2007-11-26

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L23/32 ,  H01L23/31 ,  H01L23/28 ,  H01L23/532 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/532 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5GPa or less.

Abstract translation: 一种包括芯片的器件，其包括限定一个或多个电子器件的衬底和经由夹在所述芯片和所述印刷电路板之间的一个或多个焊料元件与所述芯片电连接的印刷电路板，所述缓冲层具有 杨氏模量2.5GPa以下。

公开(公告)号：US20150262933A1

公开(公告)日：2015-09-17

申请号：US14208310

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jiun Yi Wu ,  Hsueh-Lung Cheng ,  Shou-Yi Wang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/66 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/76804 ,  H01L21/7685 ,  H01L21/76879 ,  H01L22/32 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/03416 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05091 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/20643 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

Abstract translation: 提供了半导体布置和形成方法。 半导体装置包括在至少第一电介质层和第二电介质层下面的金属迹线。 金属迹线通过第一介电层中的第一通孔和第二介电层中的第二通孔连接到球形连接。 金属轨迹在连接点处连接到测试焊盘，其中连接点在第一介电层下。 至少第一电介质层和第二电介质层上的金属迹线与金属迹线相比具有增加的稳定性和降低的对连接点，连接点，第一通孔或第二通孔中的至少一个的破裂敏感性 不在至少第一介电层和第二介电层下。

公开(公告)号：US20150221608A1

公开(公告)日：2015-08-06

申请号：US14686210

申请日：2015-04-14

Applicant: Intel Corporation

Inventor： Javier SOTO GONZALEZ ,  Charavana K. GURUMURTHY ,  Robert M. NICKERSON ,  Debendra MALLIK

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/20 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

Abstract translation: 微电子器件包括层叠安装基板，其包括裸片侧和具有设置在安装基板裸片侧的凹部中的表面光洁度层的平台侧。 导电的第一插头与表面光洁度层接触，并且导电的后续插头设置在安装衬底接地侧上，并且其电耦合到导电的第一插头并且直接设置在导电的第一插头的正下方。

公开(公告)号：US20150217409A1

公开(公告)日：2015-08-06

申请号：US14613256

申请日：2015-02-03

Applicant: Senju Metal lndustry Co., Ltd.

Inventor： Takashi AKAGAWA ,  Hiroyoshi KAWASAKI ,  Kazuhiko MATSUI ,  Yuichi KOIKEDA ,  Masaru SASAKI ,  Hiroyuki YAMASAKI ,  Takahiro ROPPONGI ,  Daisuke SOMA ,  Isamu SATO

IPC: B23K35/02 ,  B23K35/30 ,  H01B1/02 ,  C22C19/03 ,  C22C19/07 ,  H01L23/00 ,  C22C5/06

CPC classification number: B23K35/025 ,  B22F1/0062 ,  B22F1/0074 ,  B22F1/02 ,  B23K35/00 ,  B23K35/0244 ,  B23K35/3006 ,  B23K35/3033 ,  B23K35/3046 ,  C22C5/06 ,  C22C13/00 ,  C22C19/03 ,  C22C19/07 ,  H01B1/02 ,  H01L24/13 ,  H01L2224/13014 ,  H01L2224/13139 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0109 ,  H01L2924/01092 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065

Abstract: Providing an Ag ball having a low alpha dose and a high sphericity regardless of impurity elements having an amount equal to or more than a predetermined value except for Ag. In order to suppress a soft error and reduce an connection fault, a content of U is equal to or less than 5 ppb, a content of Th is equal to or less than 5 ppb, a purity is equal to or more than 99.9% but equal to or less than 99.9995%, an alpha dose is equal to or less than 0.0200 cph/cm2, a content of either Pb or Bi or a total content of both Pb and Bi is equal to or more than 1 ppm, and a sphericity is equal to or more than 0.90.

Abstract translation: 提供具有低α剂量和高球形度的Ag球，而不管除了Ag之外具有等于或大于预定值的量的杂质元素。 为了抑制软错误并减少连接故障，U的含量等于或小于5ppb，Th的含量等于或小于5ppb，纯度等于或大于99.9％，但是 等于或小于99.9995％，α剂量等于或小于0.0200cph / cm 2，Pb或Bi的含量或Pb和Bi的总含量等于或大于1ppm，并且球形度 等于或大于0.90。

公开(公告)号：US20150171063A1

公开(公告)日：2015-06-18

申请号：US14192145

申请日：2014-02-27

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Yizhang Yang ,  Mengzhi Pang

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/165 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die electrically connected to the first substrate such that the first die is directly bonded to the first substrate. The semiconductor device package assembly may include a second substrate directly bonded to a surface of the first die. The semiconductor device package assembly may include an electronic memory module. The electronic memory module may be directly bonded to the second substrate. The semiconductor device package assembly may include a thermally conductive material directly applied to the electronic memory module. The semiconductor device package assembly may include a heat spreader directly bonded to the thermally conductive material. The heat spreader may function to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side.

Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 半导体器件封装组件可以包括电连接到第一衬底的第一裸片，使得第一裸片直接结合到第一衬底。 半导体器件封装组件可以包括直接接合到第一管芯的表面的第二衬底。 半导体器件封装组件可以包括电子存储器模块。 电子存储器模块可以直接结合到第二衬底。 半导体器件封装组件可以包括直接施加到电子存储器模块的导热材料。 半导体器件封装组件可以包括直接结合到导热材料的散热器。 散热器可以起到将热量从第一模具和电子存储器模块通过散热器从第一侧传递到第二侧的功能。

公开(公告)号：US08960899B2

公开(公告)日：2015-02-24

申请号：US13627574

申请日：2012-09-26

Applicant: Google Inc.

Inventor： James Etzkorn

IPC: G02C7/02 ,  H01L23/48 ,  H01L21/56 ,  G02C7/04 ,  H01L23/00

CPC classification number: G02C11/10 ,  A61B5/6821 ,  A61B2562/12 ,  B29D11/00048 ,  B29D11/00807 ,  G02C7/04 ,  G02C7/049 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/08225 ,  H01L2224/11312 ,  H01L2224/13109 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8012 ,  H01L2224/8085 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00 ,  H01L2224/83104 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/00013 ,  H01L2924/20105 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate.

公开(公告)号：US20140175644A1

公开(公告)日：2014-06-26

申请号：US13721329

申请日：2012-12-20

Applicant: Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

Inventor： Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括将装置附接到贴片基板，其中组装的装置和贴片基板包括翘曲，将组装的装置和贴片基板附接到插入件以形成封装结构，然后在温度下回流封装结构 低于大约200摄氏度以形成基本平坦的包装结构。

公开(公告)号：US20140021605A1

公开(公告)日：2014-01-23

申请号：US13552375

申请日：2012-07-18

Applicant: Chen-Hua Yu ,  Yung Ching Chen ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Mirng-Ji Lii ,  Ming-Da Cheng

Inventor： Chen-Hua Yu ,  Yung Ching Chen ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Mirng-Ji Lii ,  Ming-Da Cheng

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/68778 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.

Abstract translation: 封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP器件包括第一封装管芯和耦合到第一封装管芯的第二封装管芯。 在第一封装模具和第二封装模具之间设置金属凸块凸块。 金属柱凸块包括一个棒状区域，一个耦合到该棒状区域的第一端的第一球形区域和一个耦合到该棒状区域的第二端的第二球形区域。 金属柱凸块包括部分嵌入焊点中的部分。