Patent search cpc:"H01L2924/04953" Page 10

91.

发明授权
Method of fabricating a chip package 有权
Title translation: 制造芯片封装的方法

公开(公告)号：US08912087B2

公开(公告)日：2014-12-16

申请号：US13563833

申请日：2012-08-01

Applicant: Josef Hirtreiter , Walter Hartner , Ulrich Wachter , Juergen Foerster

Inventor： Josef Hirtreiter , Walter Hartner , Ulrich Wachter , Juergen Foerster

IPC: H01L21/44 , H01L23/48 , H01L21/283 , H01L23/00

CPC classification number: H01L21/283 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L2224/02331 , H01L2224/02379 , H01L2224/0347 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05022 , H01L2224/05166 , H01L2224/05186 , H01L2224/05548 , H01L2224/05557 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/12105 , H01L2224/13006 , H01L2224/13024 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13164 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/35121 , H01L2924/01015 , H01L2924/01046 , H01L2924/01079 , H01L2924/014 , H01L2924/00012 , H01L2924/04941 , H01L2924/04953 , H01L2924/01074 , H01L2224/05552 , H01L2924/00

Abstract: A method for manufacturing a chip package is provided. The method includes: forming an electrically insulating material over a chip side; selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material, depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side; forming an electrically conductive structure over the electrically insulating material, wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material; and depositing a joining structure over the electrically conductive structure.

Abstract translation: 提供了一种制造芯片封装的方法。该方法包括：在芯片侧上形成电绝缘材料; 选择性地去除所述电绝缘材料的至少一部分，从而在所述电绝缘材料中形成沟槽，在所述沟槽中沉积导电材料，其中所述导电材料电连接到在所述芯片侧上形成的至少一个接触焊盘; 在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接; 以及在所述导电结构上沉积接合结构。

92.

发明申请
SEMICONDUCTOR DEVICE 有权
Title translation: 半导体器件

公开(公告)号：US20140361299A1

公开(公告)日：2014-12-11

申请号：US14465975

申请日：2014-08-22

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe

IPC: H01L21/66 , G01R31/26

CPC classification number: H01L22/32 , G01R31/26 , H01L22/14 , H01L22/20 , H01L22/30 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/02166 , H01L2224/02313 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/06133 , H01L2224/06135 , H01L2224/10 , H01L2224/1132 , H01L2224/11334 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/4911 , H01L2224/49429 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/85951 , H01L2225/0651 , H01L2225/06517 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/12041 , H01L2924/1306 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2224/48744 , H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract translation: 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

93.

发明授权
Connector design for packaging integrated circuits 有权
Title translation: 封装集成电路的连接器设计

公开(公告)号：US08901735B2

公开(公告)日：2014-12-02

申请号：US14161111

申请日：2014-01-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu , Ying Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Jing-Cheng Lin , Shang-Yun Hou , Shin-Puu Jeng

IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02 , H01L23/00 , H01L25/04 , H01L25/00 , H01L23/14 , H01L23/498

CPC classification number: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Abstract translation: 一种器件包括具有顶表面的顶部电介质层。金属柱在顶部介电层的顶表面上具有一部分。在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。焊料区域设置在金属柱上并电耦合到金属柱。

94.

发明授权
Joining electrode, method of manufacturing the same, semiconductor device, and method of manufacturing the same 有权
Title translation: 接合电极，其制造方法，半导体器件及其制造方法

公开(公告)号：US08884439B2

公开(公告)日：2014-11-11

申请号：US13352612

申请日：2012-01-18

Applicant: Kenichi Aoyagi

Inventor： Kenichi Aoyagi

IPC: H01L23/42 , H01L23/00 , H01L21/321

CPC classification number: H01L24/81 , H01L21/3212 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2224/0345 , H01L2224/03462 , H01L2224/03616 , H01L2224/0401 , H01L2224/05026 , H01L2224/05181 , H01L2224/05186 , H01L2224/05546 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/08148 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/00012 , H01L2924/04941 , H01L2924/04953 , H01L2224/05552

Abstract: Disclosed herein is a joining electrode including: an insulating layer; a recessed portion formed in the insulating layer; a covering layer formed on a side surface and a bottom surface of the recessed portion; and a joining metallic layer formed on the covering layer and having an upper surface protruding from a surface of the insulating layer.

Abstract translation: 本文公开了一种接合电极，包括：绝缘层; 形成在所述绝缘层中的凹部; 覆盖层，形成在所述凹部的侧面和底面上; 以及形成在覆盖层上并具有从绝缘层的表面突出的上表面的接合金属层。

95.

发明授权
Circuitry component and method for forming the same 有权
Title translation: 电路组件及其形成方法

公开(公告)号：US08884433B2

公开(公告)日：2014-11-11

申请号：US12545880

申请日：2009-08-24

Applicant: Mou-Shiung Lin , Chien-Kang Chou , Ke-Hung Chen

Inventor： Mou-Shiung Lin , Chien-Kang Chou , Ke-Hung Chen

IPC: H01L29/40 , H01L23/532 , H01L23/00 , H01L23/31 , H01L21/768 , H01L23/522

CPC classification number: H01L24/12 , H01L21/76801 , H01L23/3192 , H01L23/5227 , H01L23/53295 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L2224/0347 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05669 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/16227 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/45169 , H01L2224/45173 , H01L2224/45176 , H01L2224/45183 , H01L2224/48091 , H01L2224/48463 , H01L2224/48844 , H01L2224/48847 , H01L2224/48864 , H01L2224/73204 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/351 , H01L2224/48824 , H01L2924/00 , H01L2224/48869 , H01L2224/05599

Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

Abstract translation: 电路结构包括半导体衬底，半导体衬底上的第一和第二金属柱，半导体衬底上的绝缘层，并覆盖第一和第二金属柱，第一和第二金属柱上的第一和第二凸起或绝缘层。第一和第二金属柱的高度为20至300微米，其最大水平尺寸与其高度之比小于4.第一凸起的中心与第二凸起的中心之间的距离在10和250微米之间。

96.

发明申请
METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BUMP 审中-公开
Title translation: 制造具有BUMP的半导体器件的方法

公开(公告)号：US20140329382A1

公开(公告)日：2014-11-06

申请号：US14080755

申请日：2013-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： SON-KWAN HWANG , JIN-HO CHUN , BYUNG-LYUL PARK , JEONG-GI JIN , GIL-HEYUN CHOI

IPC: H01L23/00

CPC classification number: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05647 , H01L2224/05655 , H01L2224/05676 , H01L2224/05684 , H01L2224/1146 , H01L2224/11472 , H01L2224/13012 , H01L2224/13018 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/81191 , H01L2224/81815 , H01L2224/81895 , H01L2924/00012 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a photoresist pattern having a side recess on a seed metal layer and forming a plating layer having a hem using a plating process to fill the side recess.

Abstract translation: 提供一种制造半导体器件的方法。该方法包括在种子金属层上形成具有侧凹部的光致抗蚀剂图案，并且通过电镀工艺形成具有下摆的镀层以填充侧凹部。

97.

发明申请
SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME 有权
Title translation: 具有底层金属化（UBM）结构的半导体器件及其形成方法

公开(公告)号：US20140327136A1

公开(公告)日：2014-11-06

申请号：US14335084

申请日：2014-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Fu TSAI , Yian-Liang KUO , Chih-Horng CHANG

IPC: H01L23/498 , H01L23/535 , H01L21/768

CPC classification number: H01L23/49811 , H01L21/76885 , H01L21/76886 , H01L23/535 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03424 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03614 , H01L2224/03848 , H01L2224/03901 , H01L2224/03903 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/0508 , H01L2224/05084 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/1147 , H01L2224/11849 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/04941 , H01L2924/04953 , H01L2924/013 , H01L2924/01046 , H01L2924/01039 , H01L2924/01016 , H01L2924/0103 , H01L2924/01083 , H01L2924/01049 , H01L2924/01051 , H01L2924/01028 , H01L2224/034 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552

Abstract: A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.

Abstract translation: 半导体器件包括半导体衬底，覆盖半导体衬底的凸起下金属化（UBM）结构以及覆盖并电连接到UBM结构的焊料凸块。 UBM结构包括第一金属化层，其包括第一金属，第二金属化层，第二金属化层包括不同于第一金属的第二金属，以及在第一金属化层和第二金属化层之间的第一金属间化合物（IMC）层，第一IMC 层，其包含第一金属和第二金属。

98.

发明授权
Semiconductor packages with integrated antenna and methods of forming thereof 有权
Title translation: 集成天线的半导体封装及其形成方法

公开(公告)号：US08866292B2

公开(公告)日：2014-10-21

申请号：US13736641

申请日：2013-01-08

Applicant: Gottfried Beer , Maciej Wojnowski , Mehran Pour Mousavi

Inventor： Gottfried Beer , Maciej Wojnowski , Mehran Pour Mousavi

IPC: H01L23/34 , H01L23/498 , H01L21/768

CPC classification number: H01L23/49816 , H01L21/568 , H01L21/76802 , H01L21/76885 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2223/6677 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/17519 , H01L2224/211 , H01L2224/215 , H01L2224/82101 , H01L2224/96 , H01L2924/0002 , H01L2924/12042 , H01L2924/1301 , H01L2924/181 , H01Q1/2283 , H01Q9/0407 , H01Q9/16 , H01Q23/00 , H01L2224/19 , H01L2924/014 , H01L2924/01022 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/01029 , H01L2924/01055 , H01L2924/01064 , H01L2924/01044 , H01L2924/01042 , H01L2924/01015 , H01L2924/0105 , H01L2924/00012 , H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.

Abstract translation: 根据本发明的实施例，半导体封装包括具有第一主表面和相对的第二主表面的衬底。第一芯片设置在基板中。第一芯片包括在第一主表面处的多个接触垫。通孔棒设置在基板中。天线结构设置在通孔条内。

99.

发明授权
MIM decoupling capacitors under a contact pad 有权
Title translation: MIM去耦电容器在接触垫下

公开(公告)号：US08866260B2

公开(公告)日：2014-10-21

申请号：US12617314

申请日：2009-11-12

Applicant: Hau-Tai Shieh , Chen-Hui Hsieh

Inventor： Hau-Tai Shieh , Chen-Hui Hsieh

IPC: H01L21/02 , H01L23/522 , H01L23/00 , H01L49/02 , H01L27/02

CPC classification number: H01L24/06 , H01L23/5223 , H01L24/05 , H01L27/0207 , H01L28/40 , H01L2224/05093 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01044 , H01L2924/0105 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01327 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/15788 , H01L2924/19041 , H01L2924/30105 , H01L2924/00014 , H01L2924/00

Abstract: An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.

Abstract translation: 集成电路结构包括具有去耦电容器的一个或多个外部接触焊盘，例如直接形成的金属 - 绝缘体 - 金属（MIM）电容器。在一个实施例中，去耦电容器形成在第一金属化层下方，并且在另一个实施例中，去耦电容器形成在最上层的金属间介电层中。去耦电容器的底板电耦合到Vdd和Vss之一，并且去耦电容器的顶板电耦合到另一个。去耦电容器可以包括形成在外部接触焊盘下方的去耦电容阵列，并且可以包括一个或多个虚拟去耦电容器。一个或多个虚拟去耦电容器是MIM电容器，其中顶板和底板中的至少一个不电耦合到外部接触焊盘。