公开(公告)号：US09427830B2

公开(公告)日：2016-08-30

申请号：US13380123

申请日：2010-06-23

申请人： Tomohiro Uno ,  Shinichi Terashima ,  Takashi Yamada ,  Daizo Oda

发明人： Tomohiro Uno ,  Shinichi Terashima ,  Takashi Yamada ,  Daizo Oda

IPC分类号： C22C9/08 ,  B32B15/20 ,  B23K35/30 ,  B21C1/00 ,  B21C37/04 ,  B23K35/02 ,  C22C9/00 ,  C22F1/08 ,  H01L23/00

CPC分类号： B23K35/302 ,  B21C1/003 ,  B21C37/047 ,  B23K35/0261 ,  C22C9/00 ,  C22F1/08 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05624 ,  H01L2224/4321 ,  H01L2224/435 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/4851 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/85181 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20755 ,  Y10T428/2958 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00013 ,  H01L2924/01012

摘要： The present invention is a copper-based bonding wire for use in a semiconductor element. The bonding wire of the present invention can be manufactured with an inexpensive material cost, and has a superior PCT reliability in a high-humidity/temperature environment. Further, the bonding wire of the present invention exhibits: a favorable TCT reliability through a thermal cycle test; a favorable press-bonded ball shape; a favorable wedge bondability; a favorable loop formability, and so on. Specifically, the bonding wire of the present invention is a copper alloy bonding wire for semiconductor manufactured by drawing a copper alloy containing 0.13 to 1.15% by mass of Pd and a remainder comprised of copper and unavoidable impurities.

摘要翻译： 本发明是用于半导体元件的铜基接合线。 本发明的接合线可以以廉价的材料成本制造，并且在高湿度/温度环境中具有优异的PCT可靠性。 此外，本发明的接合线通过热循环试验表现出良好的TCT可靠性; 有利的压合球形; 有利的楔形粘合性; 良好的循环成形性等。 具体地，本发明的接合线是通过拉伸含有0.13〜1.15质量％的Pd，余量由铜和不可避免的杂质构成的铜合金而制造的半导体用铜合金接合线。

公开(公告)号：US20160234945A1

公开(公告)日：2016-08-11

申请号：US15021794

申请日：2014-08-27

申请人： SUMITOMO METAL MINING CO., LTD.

发明人： Hiroaki NAGATA

IPC分类号： H05K3/34 ,  B23K35/26 ,  C22C12/00 ,  H05K1/18 ,  H05K1/09

CPC分类号： H05K3/3457 ,  B23K35/26 ,  B23K35/264 ,  C22C1/02 ,  C22C1/03 ,  C22C12/00 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29113 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/09 ,  H05K1/181 ,  H05K3/341 ,  H01L2224/45099 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01032 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01052 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/20107 ,  H01L2924/00012 ,  H01L2924/00

摘要： Provided is a Bi-based solder alloy containing a specific amount of Al in Bi—Ag and having particles including a Ag—Al intermetallic compound dispersed therein, a method of bonding a Ag-plated electronic component, a bare Cu frame electronic component, an Ni-plated electronic component, or the like using the same, and an electronic component-mounted board.A Bi-based solder alloy includes Ag and Al, is substantially free of Pb, and has a Bi content of 80 mass % or more, a solidus of a melting point of 265° C. or more, and a liquidus of 390° C. or less. A content of Ag is 0.6 to 18 mass %, a content of Al is 0.1 to 3 mass %, the content of Al is 1/20 to 1/2 of the content of Ag, and particles including a Ag—Al intermetallic compound are dispersed in the solder alloy.

摘要翻译： 本发明提供一种在Bi-Ag中含有特定量的Al并具有分散在其中的Ag-Al金属间化合物的粒子的Bi系焊料合金，将Ag镀层电子部件，裸铜框电子部件， 镀镍电子部件等，以及电子部件安装板。 包含Ag和Al的Bi基焊料合金基本上不含Pb，并且Bi含量为80质量％以上，熔点为265℃以上的固相线，390℃的液相线 。 或更少。 Ag的含量为0.6〜18质量％，Al的含量为0.1〜3质量％，Al的含量为Ag的1/20〜1/2，Ag-Al金属间化合物的粒子为 分散在焊料合金中。

公开(公告)号：US20160181225A1

公开(公告)日：2016-06-23

申请号：US15012907

申请日：2016-02-02

申请人： Texas Instruments Incorporated

发明人： Kejun Zeng ,  Amit Sureshkumar Nangia

IPC分类号： H01L23/00

CPC分类号： H01L24/85 ,  H01L21/56 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/85035 ,  H01L2224/85205 ,  H01L2224/85948 ,  H01L2924/00014 ,  H01L2924/3862 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.

摘要翻译： 公开了一种制造半导体器件的方法。 提供了一种封装的半导体器件，其具有连接到铝焊盘的铜球焊接。 将包装的装置在约250℃至270℃的温度下处理至少一个循环，持续约20秒至40秒的时间。

公开(公告)号：US20160181221A1

公开(公告)日：2016-06-23

申请号：US14910355

申请日：2014-10-06

申请人： NSK LTD.

发明人： Takashi SUNAGA ,  Noboru KANEKO ,  Osamu MIYOSHI ,  Ryoichi SUZUKI

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/492 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L24/41 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L29/7393 ,  H01L29/78 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/2732 ,  H01L2224/29101 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/35847 ,  H01L2224/3701 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37611 ,  H01L2224/4001 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/4099 ,  H01L2224/4112 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84138 ,  H01L2224/8421 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/9221 ,  H01L2924/00015 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/19105 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/48 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/00013

摘要： To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed.

摘要翻译： 提供通过焊料具有高可靠性的电连接并且便宜的半导体模块。 电极接合部的与裸芯片FET的栅电极接合的面相对的基板接合部的接合面与与其他布线图案的被接合面相对的基板接合部的接合面包含 在金属板连接器的焊接期间使从熔融焊料产生的废气从放置在接合面和待接合面之间的焊料脱离的脱气释放机构。

公开(公告)号：US09368675B2

公开(公告)日：2016-06-14

申请号：US14633133

申请日：2015-02-27

申请人： NICHIA CORPORATION

发明人： Yoshikazu Takeuchi ,  Toshiaki Moriwaki ,  Atsushi Takeichi ,  Takahiro Tani

IPC分类号： H01L21/00 ,  H01L33/00 ,  H01L33/62 ,  H01L23/00

CPC分类号： H01L33/0095 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83011 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2933/0066 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/00013 ,  H01L2924/00

摘要： A method of manufacturing a light-emitting device includes flattening top portions of solder bumps disposed on a wiring substrate, disposing a light-emitting element on the solder bumps whose top portions are flattened, and heating the solder bumps to be melt and to be fused so as to provide an adhesive with which the light-emitting element is secured on the wiring substrate.

摘要翻译： 一种制造发光器件的方法包括：布置在布线基板上的焊料凸起的平坦化顶部，将发光元件设置在其顶部平坦化的焊料凸块上，并加热要熔化的焊料凸块并熔化 从而提供将发光元件固定在布线基板上的粘合剂。

公开(公告)号：US20160163806A1

公开(公告)日：2016-06-09

申请号：US14929912

申请日：2015-11-02

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takeyoshi NISHIMURA

IPC分类号： H01L29/417 ,  H01L29/10 ,  H01L23/00 ,  H01L29/78

CPC分类号： H01L29/41741 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L29/1095 ,  H01L29/417 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/7392 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48455 ,  H01L2224/4847 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/2076 ,  H01L2924/01028 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01012 ,  H01L2924/0103 ,  H01L2924/013 ,  H01L2924/01008

摘要： A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film.

摘要翻译： 可以抑制在执行半导体器件的电极层的表面的引线接合时由应力和热滞后引起的栅极阈值电压的劣化。 半导体器件包括设置在半导体芯片的表面的金属膜和与金属膜的上表面接合的引线。 金属膜具有多个晶粒，粒子的粒径基本上等于或大于金属膜的厚度。

公开(公告)号：US09331050B2

公开(公告)日：2016-05-03

申请号：US13355748

申请日：2012-01-23

申请人： Kevin J. Hess ,  Chu-Chung Lee

发明人： Kevin J. Hess ,  Chu-Chung Lee

IPC分类号： H01L23/00

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/00013

摘要： Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material. The structure may include a gold free air ball in contact with the diffusion retardant layer.

摘要翻译： 描述形成金 - 铝电互连的方法。 该方法可以包括在金和铝之间插入扩散阻挡层，扩散阻挡层包含含有基本上没有扩散阻挡材料的区域; 与扩散阻挡层，金和铝接触; 在含有材料的区域中形成金和扩散阻挡材料的合金，并在基本上不含该材料的区域中形成金 - 铝金属间化合物; 并在铝和金之间形成连续的导电路径。 提供了金 - 铝互连结构。 该结构可以包括铝合金接合焊盘和与接合焊盘接触的扩散阻挡层，扩散阻挡层包括含有基本上没有扩散阻挡材料的区域。 该结构可以包括与扩散阻挡层接触的无金空气球。

公开(公告)号：US09293436B2

公开(公告)日：2016-03-22

申请号：US14711014

申请日：2015-05-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshihiko Akiba ,  Akihiro Tobita ,  Yuki Yagyu

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L24/05 ,  H01L21/4885 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05555 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2224/05684 ,  H01L2224/16012 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2224/85375 ,  H01L2224/97 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.

摘要翻译： 一种BGA的制造方法，包括以下步骤：提供具有电极焊盘的半导体芯片; 并除去形成在每个电极焊盘的表面上的自然氧化膜。 此外，在通过去除天然氧化膜而暴露的电极焊盘的表面上形成由导电部件构成的第一膜，电线与第一膜连接，并且电线的一部分与电极焊盘接触， 在导线和电极焊盘之间的界面处形成合金层。 第一膜的晶体结构由体心立方晶格或六方密堆积晶格组成。 可以降低半导体器件的成本，同时确保半导体器件的引线接合的接合可靠性。

公开(公告)号：US20160078980A1

公开(公告)日：2016-03-17

申请号：US14888827

申请日：2014-04-04

申请人： HERAEUS MATERIALS SINGAPORE PTE., LTD.

发明人： Murali SARANGAPANI ,  Ping Ha YEUNG ,  Eugen MILKE

IPC分类号： H01B5/02 ,  H05K1/02 ,  H05K1/11

CPC分类号： H01B5/02 ,  C22C9/00 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/745 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/4321 ,  H01L2224/43985 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/85205 ,  H01L2224/859 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0213 ,  H05K1/111 ,  H01L2924/01047 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01024 ,  H01L2924/0102 ,  H01L2924/01058 ,  H01L2924/01012 ,  H01L2924/01057 ,  H01L2924/01013 ,  H01L2924/01005 ,  H01L2924/0104 ,  H01L2924/01022 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01026 ,  H01L2924/01025 ,  H01L2224/43848 ,  H01L2924/01204 ,  H01L2924/01203 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/00012 ,  H01L2924/01033 ,  H01L2924/206

摘要： The invention is related to a bonding wire containing a core having a surface. The core contains copper as a main component, an average size of crystal grains in the core is between 2.5 μm and 30 μm, and a yield strength of the bonding wire is less than 120 MPa.

摘要翻译： 本发明涉及包含具有表面的芯的接合线。 芯部以铜为主要成分，芯部的晶粒的平均粒径为2.5μm〜30μm，接合线的屈服强度小于120MPa。

公开(公告)号：US20160056072A1

公开(公告)日：2016-02-25

申请号：US14467191

申请日：2014-08-25

申请人： GLOBALFOUNDRIES, Inc.

发明人： Charles L. Arvin ,  Harry D. Cox ,  Eric D. Perfecto ,  Thomas A. Wassick

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L24/11 ,  H01L21/6835 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03849 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2224/13164 ,  H01L2924/01026 ,  H01L2924/206 ,  H01L2924/01047

摘要： A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

摘要翻译： 三维多管芯封装包括第一管芯和第二管芯。 第一个模具包括一个连接到焊料的触点。 通过将处理器粘合地附接到第二管芯的顶侧并使第二管芯的底侧变薄来减小第二管芯。 第二模具包括抑制粘合剂转移的层状冶金的多层接触。 层状冶金包括至少一层可润湿的焊料。 多层接触可以包括镍层，镍层上的铜层和铜层上的镍 - 铁层。 多层接触还可以包括镍层，镍层上的铜 - 锡层和在铜 - 锡层上的锡层。