公开(公告)号：US20120299202A1

公开(公告)日：2012-11-29

申请号：US13477524

申请日：2012-05-22

申请人： Atsushi YAMAGUCHI ,  Hideyuki TSUJIMURA ,  Hiroe KOWADA ,  Ryo KUWABARA ,  Naomichi OHASHI

发明人： Atsushi YAMAGUCHI ,  Hideyuki TSUJIMURA ,  Hiroe KOWADA ,  Ryo KUWABARA ,  Naomichi OHASHI

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L23/315 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16238 ,  H01L2224/29017 ,  H01L2224/29035 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83862 ,  H01L2224/9221 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/0665

摘要： A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity η1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity η2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30≦η2≦η1≦300 (Pa·s) and 3≦T2≦T1≦7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1≦S2.

摘要翻译： 一种半导体封装件的安装结构的制造方法，包括：在安装的半导体封装部件的外侧的基板上的位置处施加粘度1和触变指数T1的第一粘合剂; 在第一粘合剂上施加粘度为2和触变指数T2的第二粘合剂，使得第二粘合剂与半导体封装部件的外周部分接触; 并且通过随后的回流工艺形成所述硬化的第一粘合剂的第一粘合剂部分和所述硬化的第二粘合剂的第二粘合剂部分，其中所述第一和第二粘合剂满足30＆lt; 1＆nlE; 2＆nlE; 1＆nlE; 300（Pa· s和3＆nlE; T2＆nlE; T1＆nlE; 7，第一粘合部分的截面面积S1和第二粘合部分的截面面积S2相对于与基板的安装表面垂直的方向满足关系S1＆lt; lE; S2。

公开(公告)号：US20080061431A1

公开(公告)日：2008-03-13

申请号：US11834724

申请日：2007-08-07

申请人： Shinichi Fujiwara ,  Masahide Harada ,  Hideto Yoshinari ,  Shosaku Ishihara ,  Shiro Yamashita ,  Isamu Yoshida ,  Ukyo Ikeda

发明人： Shinichi Fujiwara ,  Masahide Harada ,  Hideto Yoshinari ,  Shosaku Ishihara ,  Shiro Yamashita ,  Isamu Yoshida ,  Ukyo Ikeda

IPC分类号： H01L23/34

CPC分类号： H01L23/3735 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/26165 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83136 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/9221 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/84

摘要： A semiconductor module of the present invention comprises a first conductive layer (film) and a second conductive layer (film) which are separately formed on the main surface of a packed substrate, a thermal diffusion plate connected by solder to the upper surface of the first conductive layer, a semiconductor element connected by solder to the upper surface of the thermal diffusion plate, and a lead having one end connected by solder to the second conductive layer and the other end connected by solder to the semiconductor element, wherein the outer periphery of the connected region where the semiconductor element is connected by solder to the upper surface of the thermal diffusion plate is formed with protrusion parts protruding up from the connecting region and a turning of the semiconductor element in the upper surface of the thermal diffusion plate in the solder connecting process is suppressed by the protrusion parts.

摘要翻译： 本发明的半导体模块包括在填充基板的主表面上分别形成的第一导电层（膜）和第二导电层（膜），通过焊料与第一导电层（膜）的上表面连接的热扩散板 导电层，通过焊料连接到热扩散板的上表面的半导体元件，以及引线，其一端通过焊料连接到第二导电层，另一端通过焊料连接到半导体元件，其中外周边 半导体元件通过焊料连接到热扩散板的上表面的连接区域形成有从连接区域突出的突出部分和在焊料中的热扩散板的上表面中的半导体元件的转动 连接过程被突出部分抑制。

公开(公告)号：US09633967B2

公开(公告)日：2017-04-25

申请号：US14910355

申请日：2014-10-06

申请人： NSK Ltd.

发明人： Takashi Sunaga ,  Noboru Kaneko ,  Osamu Miyoshi ,  Ryoichi Suzuki

IPC分类号： H01L29/66 ,  H01L27/08 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L23/373 ,  H01L23/498 ,  H01L23/492 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L24/41 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L29/7393 ,  H01L29/78 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/2732 ,  H01L2224/29101 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/35847 ,  H01L2224/3701 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37611 ,  H01L2224/4001 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/4099 ,  H01L2224/4112 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84138 ,  H01L2224/8421 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/9221 ,  H01L2924/00015 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/19105 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/48 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/00013

摘要： To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed.

公开(公告)号：US09368472B2

公开(公告)日：2016-06-14

申请号：US13955246

申请日：2013-07-31

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Baptiste Goubault de Brugiere ,  Alexis Bedoin

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/1416 ,  H01L2224/14505 ,  H01L2224/1601 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81099 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/8183 ,  H01L2224/83102 ,  H01L2224/9221 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0001 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00011

摘要： The invention relates to a flip-chip assembly process for connecting two microelectronic components (1, 2) to each other. According to the invention, it is possible either to proportion the spacers (24) so that they are smaller than the interconnect bumps (22) or to oversize the latter so that their deformation, after having been plastic during the insertion of connective inserts (12), returns to the elastic regime once assembly contact between components (1,2) has been reached. Thanks to the invention, it is possible to control with great precision the gap between the two components during their assembly, and this without adding any additional steps to their manufacturing or to the assembly process.

摘要翻译： 本发明涉及一种用于将两个微电子部件（1,2）彼此连接的倒装芯片组合工艺。 根据本发明，可以使间隔物（24）比例比互连凸块（22）小，或者使间隔件（24）的尺寸小于后者，使得它们在插入连接插入件（12）期间已经塑性之后变形 ），一旦达到组件（1,2）之间的组装接触，就返回到弹性状态。 由于本发明，可以非常精确地控制两个部件在其组装期间的间隙，并且这不会在其制造或组装过程中增加任何附加步骤。

公开(公告)号：US09324607B2

公开(公告)日：2016-04-26

申请号：US14815751

申请日：2015-07-31

申请人： AVOGY, INC.

发明人： Patrick James Lazlo Hyland ,  Brian Joel Alvarez ,  Donald R. Disney

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L23/528 ,  H01L29/20 ,  H01L23/532 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/495 ,  H01L23/482 ,  H01L23/00

CPC分类号： H01L21/7685 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/76865 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/528 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0518 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/9221 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/03

摘要： A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.

公开(公告)号：US20160079222A1

公开(公告)日：2016-03-17

申请号：US14842630

申请日：2015-09-01

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takao SATO

IPC分类号： H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L24/17 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03334 ,  H01L2224/0348 ,  H01L2224/03828 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05186 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05686 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13186 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/14 ,  H01L2924/1438 ,  H01L2924/3511 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2924/07025 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0332

摘要： A semiconductor device includes a chip package including plurality of stacked semiconductor chips, a sealing layer covering at least an upper surface of the chip package, a plurality of first conductive elements disposed on the chip package and exposed on an upper surface of the sealing layer, and a plurality of second conductive elements, each being disposed on one of the exposed surfaces of the first conductive elements.

摘要翻译： 一种半导体器件包括：芯片封装，包括多个层叠的半导体芯片，至少覆盖芯片封装的上表面的密封层;多个第一导电元件，设置在芯片封装上并暴露在密封层的上表面; 以及多个第二导电元件，每个第二导电元件设置在第一导电元件的暴露表面之一上。

公开(公告)号：US20150342074A1

公开(公告)日：2015-11-26

申请号：US14435682

申请日：2013-10-25

申请人： NSK LTD.

发明人： Takashi SUNAGA ,  Noboru KANEKO ,  Osamu MIYOSHI

IPC分类号： H05K7/02

CPC分类号： H05K7/02 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/35847 ,  H01L2224/3701 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/48 ,  H01L2224/73263 ,  H01L2224/77272 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/85 ,  H01L2224/9221 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/1031 ,  H05K2201/10409 ,  Y02P70/611 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/33 ,  H01L2924/00012 ,  H01L2924/00

摘要： To provide a semiconductor module capable of shortening of the manufacturing tact time, reducing the manufacturing costs, and improving assembility. A semiconductor module (30) includes substrate (31) made of metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on a wiring pattern (33a) via a solder (34a); and a metal plate connector (36a, 36b) jointing an electrode (S, G) of the bare-chip transistor (35) and a wiring pattern (33b, 33c) via a solder (34b, 34c). The metal plate connector (36a, 36b) has a bridge shape, and has a flat surface and a center of gravity at a middle portion of the component.

摘要翻译： 提供能够缩短制造节拍时间，降低制造成本，提高组装性的半导体模块。 半导体模块（30）包括由金属制成的基板（31），形成在基板（31）上的绝缘层（32），形成在绝缘层（32）上的多个布线图案（33a〜33d） 通过焊料（34a）安装在布线图案（33a）上的芯片晶体管（35）; 以及通过焊料（34b，34c）将裸芯片晶体管（35）的电极（S，G）和布线图案（33b，33c）接合的金属板连接器（36a，36b）。 金属板连接器（36a，36b）具有桥接形状，并且在部件的中间部分具有平坦表面和重心。

公开(公告)号：US09165872B2

公开(公告)日：2015-10-20

申请号：US14523066

申请日：2014-10-24

申请人： SFI Electronics Technology Inc.

发明人： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Hong-Zong Xu

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/48

摘要： A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection.

摘要翻译： 由于不含外部引脚引脚的新颖的芯片尺寸二极管封装小型化，像芯片尺寸外观，以提高尺寸精度，使得二极管封装由自动化设备适当地生产以获得自动批量生产; 所生成的二极管封装可以包含一个或多个二极管芯片，以增加在应用中更有用的通用功能，例如作为SMT二极管封装或阵列型SMT二极管制造的，以及由于不含含铅材料制成的本二极管封装 符合环保要求。

公开(公告)号：US20150097275A1

公开(公告)日：2015-04-09

申请号：US14500179

申请日：2014-09-29

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Atsushi IMAI ,  Yoshiaki KOMINAMI ,  Takashi USHIJIMA

IPC分类号： H01L29/06 ,  H01L21/288 ,  H01L21/283 ,  H01L29/41

CPC分类号： H01L29/0657 ,  H01L21/283 ,  H01L21/288 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L29/41 ,  H01L2224/02126 ,  H01L2224/0331 ,  H01L2224/03312 ,  H01L2224/03418 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04026 ,  H01L2224/05011 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83801 ,  H01L2224/9221 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

摘要： A semiconductor device includes a substrate, a substrate-side electrode layer, an intermediate electrode layer, and a front-side electrode layer. The substrate includes a semiconductor layer and a projection portion, the projection portion being formed on a surface of the semiconductor layer. The substrate-side electrode layer is provided on the projection portion. The intermediate electrode layer extends from on a part of the substrate-side electrode layer, which part of the substrate-side electrode layer is located on the projection portion, to just above a region of the substrate in which region the projection portion is not provided. The front-side electrode layer is provided on a surface of the intermediate electrode layer. A Young's modulus E1 of the substrate-side electrode layer, a Young's modulus E2 of the intermediate electrode layer, and a Young's modulus E3 of the front-side electrode layer satisfy a relationship of E3>E1>E2.

摘要翻译： 半导体器件包括衬底，衬底侧电极层，中间电极层和正面电极层。 基板包括半导体层和突出部分，突出部分形成在半导体层的表面上。 基板侧电极层设置在突起部上。 中间电极层从基板侧电极层的基板侧电极层的位于突出部的一部分的一部分延伸到基板的不在突出部未设置的区域的正上方 。 前侧电极层设置在中间电极层的表面上。 基板侧电极层的杨氏模量E1，中间电极层的杨氏模量E2和前侧电极层的杨氏模量E3满足E3> E1> E2的关系。

公开(公告)号：US08975117B2

公开(公告)日：2015-03-10

申请号：US13369059

申请日：2012-02-08

申请人： Ralf Otremba ,  Fong Lim ,  Abdul Rahman Mohamed ,  Chooi Mei Chong ,  Ida Fischbach ,  Xaver Schloegel ,  Juergen Schredl ,  Josef Hoeglauer

发明人： Ralf Otremba ,  Fong Lim ,  Abdul Rahman Mohamed ,  Chooi Mei Chong ,  Ida Fischbach ,  Xaver Schloegel ,  Juergen Schredl ,  Josef Hoeglauer

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/95 ,  H01L2224/04026 ,  H01L2224/05553 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/2732 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/33181 ,  H01L2224/3512 ,  H01L2224/352 ,  H01L2224/37099 ,  H01L2224/37111 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/37572 ,  H01L2224/376 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/37669 ,  H01L2224/40095 ,  H01L2224/40101 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40491 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/77272 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84469 ,  H01L2224/84801 ,  H01L2224/84825 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2224/37599

摘要： A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.

摘要翻译： 一种方法包括提供具有第一主表面和第二主表面的半导体芯片。 将半导体芯片放置在载体上，其中半导体芯片的第一主表面面向载体。 第一层焊料材料设置在第一主表面和载体之间。 包括第一接触区域的接触夹子被放置在半导体芯片上，其中第一接触区域面对半导体芯片的第二主表面。 第二层焊料材料设置在第一接触区域和第二主表面之间。 此后，将热量施加到第一和第二层焊料材料，以在载体，半导体芯片和接触夹之间形成扩散焊料接合​​。