公开(公告)号：US20170025327A1

公开(公告)日：2017-01-26

申请号：US15205693

申请日：2016-07-08

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Ali Salih ,  Prasad Venkatraman ,  Chun-Li Liu

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4951 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49544 ,  H01L23/49562 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/0916 ,  H01L2224/09181 ,  H01L2224/80001

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

公开(公告)号：US09508625B2

公开(公告)日：2016-11-29

申请号：US14242114

申请日：2014-04-01

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L23/492 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49572 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/09 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor die package includes first, second and third metal blocks insulated from one another. The first metal block has a thinner inner section, a first thicker outer section at a first end of the thinner inner section and a second thicker outer section at a second end of the thinner inner section opposing the first end. The second metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. The third metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. A semiconductor die has a first terminal attached to the thinner inner section of the first metal block, a second terminal attached to the thinner inner section of the second metal block, and a third terminal attached to the thinner inner section of the third metal block.

Abstract translation: 半导体管芯封装包括彼此绝缘的第一，第二和第三金属块。 第一金属块具有更薄的内部部分，在较薄内部部分的第一端处的第一较厚外部部分和在较薄内部部分的与第一端部相对的第二端处的第二较厚外部部分。 第二金属块具有较厚的外部部分和从较厚的外部部分向内突出的较薄的内部部分。 第三金属块具有较厚的外部部分和从较厚的外部部分向内突出的较薄的内部部分。 半导体管芯具有附接到第一金属块的较薄内部的第一端子，附接到第二金属块的较薄内部的第二端子和附接到第三金属块的较薄内部的第三端子。

公开(公告)号：US09449837B2

公开(公告)日：2016-09-20

申请号：US14657354

申请日：2015-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L21/00 ,  H01L21/311 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/48 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/80001 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00014

Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

Abstract translation: 本文公开了具有设置在第一半导体衬底上的第一再分布层（RDL）和设置在第二半导体衬底上的第二RDL的封装。 第一个RDL被绑定到第二个RDL。 封装还包括布置在第二RDL上并围绕第一RDL和第一半导体衬底的绝缘膜。 导电元件设置在第一RDL中。 通孔从绝缘膜的顶表面延伸穿过第一半导体衬底到导电元件，并且间隔物设置在第一半导体衬底和通孔之间。 间隔物延伸穿过第一半导体衬底。

公开(公告)号：US09142532B2

公开(公告)日：2015-09-22

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo Suga ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  B23K31/02 ,  B23K37/00 ,  B23K37/04 ,  H01L21/66 ,  H01L25/10 ,  H01L23/10 ,  H01L21/683

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US09082879B2

公开(公告)日：2015-07-14

申请号：US14622869

申请日：2015-02-15

Applicant: IXYS Corporation

Inventor： Nathan Zommer

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/373

CPC classification number: H01L24/83 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/5385 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/0381 ,  H01L2224/05124 ,  H01L2224/05639 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08245 ,  H01L2224/09181 ,  H01L2224/27312 ,  H01L2224/2745 ,  H01L2224/29139 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80439 ,  H01L2224/8084 ,  H01L2224/80895 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05432 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/20107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80

Abstract: A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Abstract translation: 封装的功率器件不涉及软焊料，无引线接合。 两个直接结合金属的陶瓷基板组件（例如直接键合铝（DBA））基底的直接结合的金属层设置有烧结的银焊盘。 将银纳米颗粒糊剂施加到模具前侧的焊盘上，并且将该糊料烧结以形成银焊盘。 由蒸发过程形成的银覆盖了模具的背面。 模具被压在两个DBA之间，使得在管芯的前侧上的烧结银焊盘和一个DBA的相应的烧结银焊盘之间形成直接的银 - 银键，并且使得直接的银 - 银 在模具的背面银和另一个DBA的烧结银焊盘之间形成结合。 在铅成型，引线和封装之后，成品设备在外部封装表面上露出两个DBA的陶瓷。

公开(公告)号：US20140183716A1

公开(公告)日：2014-07-03

申请号：US14144587

申请日：2013-12-31

Applicant: IXYS Corporation

Inventor： Nathan Zommer

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/5385 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/0381 ,  H01L2224/05124 ,  H01L2224/05639 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08245 ,  H01L2224/09181 ,  H01L2224/27312 ,  H01L2224/2745 ,  H01L2224/29139 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80439 ,  H01L2224/8084 ,  H01L2224/80895 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05432 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/20107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80

Abstract: A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Abstract translation: 封装的功率器件不涉及软焊料，无引线接合。 两个直接结合金属的陶瓷基板组件（例如直接键合铝（DBA））基底的直接结合的金属层设置有烧结的银焊盘。 将银纳米颗粒糊剂施加到模具前侧的焊盘上，并且将该糊料烧结以形成银焊盘。 由蒸发过程形成的银覆盖了模具的背面。 模具被压在两个DBA之间，使得在管芯的前侧上的烧结银焊盘和一个DBA的相应的烧结银焊盘之间形成直接的银 - 银键，并且使得直接的银 - 银 在模具的背面银和另一个DBA的烧结银焊盘之间形成结合。 在铅成型，引线和封装之后，成品设备在外部封装表面上露出两个DBA的陶瓷。

公开(公告)号：US08704358B2

公开(公告)日：2014-04-22

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L23/04

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10μm，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连电平的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US20130062761A1

公开(公告)日：2013-03-14

申请号：US13228768

申请日：2011-09-09

Applicant: Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

Inventor： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/52 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06515 ,  H01L2224/09181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

公开(公告)号：US12068299B2

公开(公告)日：2024-08-20

申请号：US17580370

申请日：2022-01-20

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

公开(公告)号：US20240079391A1

公开(公告)日：2024-03-07

申请号：US18152451

申请日：2023-01-10

Applicant: Taiwan Semiconductor Mqanufacturing Co., Ltd.

Inventor： Chia-Hao Hsu ,  Jian-Wei Hong ,  Kuo-Chiang Ting ,  Sung-Feng Yeh

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H10B80/00 ,  H01L23/538 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/08237 ,  H01L2224/09181

Abstract: In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.