公开(公告)号：US20170229413A1

公开(公告)日：2017-08-10

申请号：US15498659

申请日：2017-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13541 ,  H01L2224/1405 ,  H01L2224/141 ,  H01L2224/16105 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

摘要： A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

公开(公告)号：US09721916B2

公开(公告)日：2017-08-01

申请号：US15255963

申请日：2016-09-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jung Wei Cheng ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC分类号： H01L23/00 ,  H01L23/544 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/14 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0214 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/14132 ,  H01L2224/14134 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

公开(公告)号：US20170213810A1

公开(公告)日：2017-07-27

申请号：US15326401

申请日：2015-11-24

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： Wanchun DING

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/50 ,  H01L21/56 ,  H01L21/563 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/1162 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00

摘要： The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip. The first chip and the second chip are disposed face-to-face, and the filling layer is formed between the first chip and the second chip. The solder ball is mounted on the connecting member. A certain height difference is formed between the solder ball and the second chip, such that a flip packaging of the chip is realized while the chip is not destroyed. The second chip will not be destroyed during the flip packaging, thereby reducing the processing risks.

公开(公告)号：US09711475B2

公开(公告)日：2017-07-18

申请号：US14879710

申请日：2015-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

摘要： A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

公开(公告)号：US09704819B1

公开(公告)日：2017-07-11

申请号：US15084442

申请日：2016-03-29

申请人： Hong Kong Applied Science and Technology Research Institute Co. Ltd.

发明人： Ziyang Gao ,  Ya Lv

IPC分类号： H01L23/34 ,  H05K7/10 ,  H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L21/66 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L22/20 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/105 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27334 ,  H01L2224/27849 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8109 ,  H01L2224/81192 ,  H01L2224/83024 ,  H01L2224/8309 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92242 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/81

摘要： A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.

公开(公告)号：US20170170149A1

公开(公告)日：2017-06-15

申请号：US15431649

申请日：2017-02-13

申请人： Micron Technology, Inc.

发明人： Seng Kim Ye ,  Hong Wan Ng

IPC分类号： H01L25/065 ,  G06F13/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0657 ,  G06F13/1668 ,  G06F13/1694 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/04 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/13083 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81855 ,  H01L2224/81856 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83874 ,  H01L2224/92227 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/83101 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/83

摘要： Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.

公开(公告)号：US20170125319A1

公开(公告)日：2017-05-04

申请号：US15340915

申请日：2016-11-01

申请人： ROHM CO., LTD.

发明人： Hideaki YANAGIDA

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L21/4853 ,  H01L23/053 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13083 ,  H01L2224/81193 ,  H01L2924/15156

摘要： The present invention provides an electronic component in which a molding resin completely fills the space between a chip component and a mounting substrate, thereby avoiding the corrosion of the chip component and mounting substrate. The electronic component includes an interposer as an example of a mounting substrate and a chip component. The interposer is disposed with a first wiring film and a second wiring film. The chip component is interposed between a first connection electrode and a second connection electrode so as to electrically and mechanically connect the first wiring film and the second wiring film. The first connection electrode and the second connection electrode are shaped as pins mounted upright from the first wiring film and second wiring film toward the chip component such that the chip component floats above the interposer and is connected to the first wiring film and the second wiring film.

公开(公告)号：US09633939B2

公开(公告)日：2017-04-25

申请号：US15049872

申请日：2016-02-22

申请人： Amkor Technology, Inc.

发明人： Do Hyung Kim ,  Dae Joon Park ,  See Won Kim ,  Jung Soo Park

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/8392 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2224/03 ,  H01L2224/11

摘要： A semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a cover layer that enhances reliability of the semiconductor packages.

公开(公告)号：US09620390B2

公开(公告)日：2017-04-11

申请号：US14993714

申请日：2016-01-12

申请人： Silex Microsystems AB

发明人： Thorbjorn Ebefors ,  Edvard Kalvesten ,  Tomas Bauer

IPC分类号： B81B7/00 ,  H01L23/04 ,  H01L23/498 ,  H01L23/64 ,  H01L23/66 ,  H01L21/50 ,  H01L21/683 ,  H01L23/552 ,  H01L23/58 ,  H01L21/78 ,  H01L21/768 ,  H01L23/10 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L21/50 ,  B81B7/007 ,  B81B2207/095 ,  B81C1/00301 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29018 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

公开(公告)号：US20170098607A1

公开(公告)日：2017-04-06

申请号：US15378622

申请日：2016-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yu Lu ,  Hsien-Pin Hu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Tzuan-Horng Liu ,  Shih-Wen Huang ,  Chun Hua Chang

IPC分类号： H01L23/525 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/5256 ,  H01L21/4846 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78

摘要： Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.