公开(公告)号：US09281457B2

公开(公告)日：2016-03-08

申请号：US13910245

申请日：2013-06-05

申请人： Nichia Corporation

发明人： Satoshi Shirahama

IPC分类号： H01L21/44 ,  H01L21/00 ,  H01L33/52 ,  H01L23/495 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L33/52 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L33/62 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20752 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/4554

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

公开(公告)号：US09269683B2

公开(公告)日：2016-02-23

申请号：US14200613

申请日：2014-03-07

申请人： International Business Machines Corporation

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/12 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

摘要： Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

摘要翻译： 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US09263301B2

公开(公告)日：2016-02-16

申请号：US13607204

申请日：2012-09-07

申请人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

发明人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16265 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.

摘要翻译： 半导体管芯具有安装在形成在载体上的多个可湿性接触焊盘上的第一和第二分立半导体部件。 导电柱形成在可湿性接触垫上。 半导体管芯通过第一分立元件安装到导电柱上。 导电柱提供半导体管芯的垂直间隔作为第一分立元件的余量。 第二分立元件设置在半导体管芯的占位面之外。 可以通过半导体管芯形成导电TSV。 密封剂沉积在半导体管芯和第一和第二分立元件上。 可湿式接触垫在封装期间减少管芯和分立元件的移动。 去除半导体管芯的后表面的一部分以减小封装厚度。 在密封剂和半导体管芯上形成互连结构。 第三分立半导体部件可以安装在半导体管芯上。

公开(公告)号：US20160035691A1

公开(公告)日：2016-02-04

申请号：US14784127

申请日：2014-03-27

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Koji YAMAZAKI ,  Takeshi ARAKI

IPC分类号： H01L23/00 ,  B23K35/30 ,  C22C5/06

CPC分类号： H01L24/49 ,  B23K20/004 ,  B23K35/3006 ,  C22C5/06 ,  H01L23/49 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/26175 ,  H01L2224/2733 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/32507 ,  H01L2224/4501 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4516 ,  H01L2224/48225 ,  H01L2224/48499 ,  H01L2224/48507 ,  H01L2224/49173 ,  H01L2224/83011 ,  H01L2224/83014 ,  H01L2224/8309 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/85801 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of Ag3Sn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer.

摘要翻译： 半导体装置包括：夹在形成于安装基板或电路基板上的第一Ag层与形成在半导体元件上的第二Ag层之间的合金层，其中，所述合金层含有由所述第一Ag的Ag成分形成的Ag 3 Sn的金属间化合物， Ag层和第二Ag层和Sn，并且其中包含Ag的多个布线从合金层的面向外周延伸设置。

公开(公告)号：US09252373B2

公开(公告)日：2016-02-02

申请号：US14704334

申请日：2015-05-05

申请人： Michael A. Tischler ,  Philippe Schick ,  Ian Ashdown ,  Calvin Wade Sheen ,  Paul Jungwirth

发明人： Michael A. Tischler ,  Philippe Schick ,  Ian Ashdown ,  Calvin Wade Sheen ,  Paul Jungwirth

IPC分类号： H01L33/00 ,  H01L21/00 ,  H01L51/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： F21K9/66 ,  F21K9/20 ,  F21K9/275 ,  F21K9/278 ,  F21K9/64 ,  F21K9/65 ,  F21V3/02 ,  F21V9/30 ,  F21V23/003 ,  F21V23/02 ,  F21V29/74 ,  F21Y2115/10 ,  G02F1/133603 ,  H01L23/367 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0753 ,  H01L27/156 ,  H01L31/0468 ,  H01L33/0025 ,  H01L33/06 ,  H01L33/08 ,  H01L33/28 ,  H01L33/30 ,  H01L33/32 ,  H01L33/36 ,  H01L33/483 ,  H01L33/486 ,  H01L33/502 ,  H01L33/505 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L51/0097 ,  H01L2224/06102 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/10321 ,  H01L2924/10322 ,  H01L2924/10323 ,  H01L2924/10324 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/381 ,  H02S30/00 ,  H05B33/0854 ,  H05B37/0218 ,  H05B37/0227 ,  H05B37/0245 ,  H05K1/189 ,  H05K3/323 ,  H05K2201/09036 ,  H05K2201/10106 ,  H05K2203/302 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01051 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.

公开(公告)号：US09240384B2

公开(公告)日：2016-01-19

申请号：US13621804

申请日：2012-09-17

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Qing Zhang ,  Haijing Cao

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/05552

摘要： A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

摘要翻译： 半导体器件具有形成在衬底上的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 第二绝缘层在第二绝缘材料的表面和第二导电层的表面之间具有侧壁。 在第二绝缘层和第二导电层的表面上形成保护层。 保护层遵循第二绝缘层和第二导电层的表面和侧壁的轮廓。 在第二导电层的表面上形成凸块，并且与第二绝缘层相邻的部分形成保护层。 保护层保护第二绝缘层。

公开(公告)号：US09236365B2

公开(公告)日：2016-01-12

申请号：US14275678

申请日：2014-05-12

申请人： Invensas Corporation

发明人： Paul W. Sanders ,  Robert E. Jones ,  Michael F. Petras ,  Chandrasekaram Ramiah

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/58 ,  H01L27/06

CPC分类号： H01L25/162 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/58 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0296 ,  H01L27/0629 ,  H01L28/00 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16503 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/13099

摘要： Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

摘要翻译： 使用集成无源器件（IPD）形成3-D IC的方法包括通过穿通基板通孔（TSV）耦合的单独预制基板堆叠。 有源器件（AD）衬底在其上部具有接触。 隔离器衬底被结合到AD衬底上，使得隔离器衬底中的TSV耦合到AD衬底上的触点。 IPD衬底接合到隔离器衬底，使得其中的TSV耦合到隔离器衬底上的互连区和/或其中的TSV。 IPD基板的IPD通过IPD和隔离器基板中的TSV耦合到AD基板中的设备。 隔离器基板提供优异的IPD与AD串扰衰减，同时允许每个基板具有小的高纵横比TSV，从而有助于高电路封装密度和高效制造。

公开(公告)号：US09219045B2

公开(公告)日：2015-12-22

申请号：US14160796

申请日：2014-01-22

申请人： STATS ChipPAC, Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

摘要翻译： 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有轨迹线和集成凸块焊盘的衬底。 导电凸块材料沉积在衬底凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得凸块材料设置在管芯凸块焊盘和衬底凸块焊盘之间。 凸块材料在芯片凸块焊盘或基板凸块焊盘周围没有焊接掩模回流以形成互连。 凸块材料在管芯凸块焊盘或衬底凸块焊盘的占用面积内自我限制。 在回流之前，凸起材料可以浸入助熔剂溶液中以增加润湿性。 或者，互连包括不可熔基底和可熔盖。 选择凸起材料的体积，使得表面张力在回流期间保持凸块内的凸起材料的自我约束。

公开(公告)号：US09214444B2

公开(公告)日：2015-12-15

申请号：US14399003

申请日：2013-05-07

申请人： Heraeus Materials Technology GmbH & Co. KG

发明人： Eugen Milke ,  Peter Prenosil ,  Sven Thomas

IPC分类号： H01L23/00 ,  H01B1/02 ,  B21C1/00 ,  B21C9/00 ,  B32B15/01 ,  H01L25/07 ,  H01L25/16

CPC分类号： H01L24/48 ,  B21C1/003 ,  B21C9/00 ,  B32B15/01 ,  H01B1/023 ,  H01B1/026 ,  H01L24/43 ,  H01L24/45 ,  H01L24/85 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/43 ,  H01L2224/4321 ,  H01L2224/4382 ,  H01L2224/43848 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45033 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45624 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16151 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/207 ,  H01L2924/2075 ,  Y10T29/49117 ,  Y10T428/1275 ,  H01L2924/01028 ,  H01L2924/01014 ,  H01L2924/01012 ,  H01L2924/01008 ,  H01L2924/01205 ,  H01L2924/01204 ,  H01L2924/01203 ,  H01L2924/01201 ,  H01L2924/01206 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2224/05599 ,  H01L2924/00013 ,  H01L2924/01049

摘要： A ribbon, preferably a bonding ribbon for bonding in microelectronics, contains a first layer containing copper, a coating layer containing aluminum superimposed over the first layer, and an intermediate layer. In a cross-sectional view of the ribbon, the area share of the first layer is from 50 to 96% and the aspect ratio between the width and the height of the ribbon in a cross-sectional view is from 0.03 to less than 0.8. The ribbon has a cross-sectional area of 25,000 μm2 to 800,000 μm2. The intermediate layer contains at least one intermetallic phase containing materials of the first and coating layers. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing the wire, to a propelled device comprising said electric device and to a process of connecting two elements through the wire by wedge-bonding.

摘要翻译： 带，优选用于在微电子学中结合的粘合带包含含有铜的第一层，包含叠加在第一层上的铝的涂层和中间层。 在带的横截面视图中，第一层的面积份额为50至96％，横截面视图中的带的宽度和高度之间的纵横比为0.03至小于0.8。 带的截面积为25,000μm2至800,000μm2。 中间层含有至少一种包含第一层和涂层的材料的金属间相。 本发明还涉及一种用于将由该工艺获得的线材制成的线材制造到包含该线材的电气装置的方法，该方法包括所述电气装置的推进装置以及通过楔形连接器将两个元件通过导线连接的过程， 粘接。

公开(公告)号：US09214442B2

公开(公告)日：2015-12-15

申请号：US11688050

申请日：2007-03-19

申请人： Karsten Guth ,  Holger Torwesten

发明人： Karsten Guth ,  Holger Torwesten

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/07

CPC分类号： H01L24/32 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.

摘要翻译： 在功率半导体模块中，连续并且固定地连接有含铜的第一焊接对象，连接层和含铜的第二焊接对象。 连接层具有至少90重量％的金属间铜 - 锡相的一部分。 为了制造这样的功率半导体模块，焊接对象和布置在其间的焊料彼此以预定压力彼此压紧，并且焊料熔化。 在预定时间段结束之后，扩散的铜和来自液态焊料的锡形成包含金属间铜 - 锡相的连接层，该连接层的至少90％是由焊料层形成的连接层。