公开(公告)号：US09704943B2

公开(公告)日：2017-07-11

申请号：US14462490

申请日：2014-08-18

申请人： XINTEC INC.

发明人： Wei-Ming Lai ,  Yu-Wen Hu

IPC分类号： H01L27/08 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/64 ,  H01L23/532

CPC分类号： H01L28/10 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11825 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1355 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1206

摘要： A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

公开(公告)号：US20170133346A1

公开(公告)日：2017-05-11

申请号：US15413058

申请日：2017-01-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Hsien-Wei Chen ,  Hung-An Teng ,  Wei-Cheng Wu

IPC分类号： H01L23/00 ,  H01L25/065 ,  C23C14/34 ,  C23C18/32 ,  C23C18/42 ,  C23C14/16 ,  H01L25/00 ,  B23K1/00

CPC分类号： H01L24/81 ,  B23K1/0016 ,  C23C14/165 ,  C23C14/34 ,  C23C18/32 ,  C23C18/42 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/10125 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

公开(公告)号：US20170103945A1

公开(公告)日：2017-04-13

申请号：US15384966

申请日：2016-12-20

申请人： TOPPAN PRINTING CO., LTD.

发明人： Akane KOBAYASHI ,  Yoshito AKUTAGAWA

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  C09J7/02 ,  H01L23/00

CPC分类号： H01L23/49838 ,  C09J7/22 ,  C09J201/00 ,  C09J2203/326 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/00 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01322 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2221/68304 ,  H01L21/56 ,  H01L2221/68381

摘要： A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.

公开(公告)号：US09613934B2

公开(公告)日：2017-04-04

申请号：US14621936

申请日：2015-02-13

申请人： INTEL CORPORATION

发明人： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  C09J9/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US09576922B2

公开(公告)日：2017-02-21

申请号：US14702984

申请日：2015-05-04

申请人： GLOBALFOUNDRIES INC.

发明人： Thomas J. Brunschwiler ,  Eric D. Perfecto ,  Jonas Zuercher

IPC分类号： H01L23/00 ,  B23K1/00 ,  B23K31/02

CPC分类号： H01L24/10 ,  B23K1/0016 ,  B23K1/0053 ,  B23K1/008 ,  B23K1/012 ,  B23K1/20 ,  B23K31/02 ,  B23K35/02 ,  B23K2101/42 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13687 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81909 ,  H01L2224/81911 ,  H01L2224/8192 ,  H01L2224/81986 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81948

摘要： A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

摘要翻译： 一种形成用于半导体器件的堆叠表面布置的方法包括：将第一表面与第二表面焊接在一起，所述焊料凸块包括基本上纯的第一金属; 将第二金属的纳米颗粒沉积到所述焊料凸块的表面上; 执行退火操作以在所述焊料凸块的表面上形成所述第二金属的膜; 以及执行回流或第二退火操作以将焊料凸块从基本上纯的第一金属转变为第一金属和第二金属的合金。

公开(公告)号：US20160372436A1

公开(公告)日：2016-12-22

申请号：US15255963

申请日：2016-09-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jung Wei Cheng ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L25/065

CPC分类号： H01L24/14 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0214 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/14132 ,  H01L2224/14134 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

公开(公告)号：US20160358875A1

公开(公告)日：2016-12-08

申请号：US15239745

申请日：2016-08-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Yu-Hsiang HSIAO ,  Chiu-Wen LEE ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC分类号： H01L23/00 ,  H01L25/00 ,  C22C9/02 ,  B23K35/26 ,  B23K1/00 ,  C22C13/00 ,  H01L25/065 ,  B23K35/30

CPC分类号： H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

摘要翻译： 半导体器件包括第一电路层，邻近第一电路层设置的铜柱，第二电路层和焊料层。 第二电路层包括电接触和设置在电接触上的表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁剂层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的两种或更多种的组合，第二IMC包括金和锡的组合，钯的组合 和锡，或两者。

公开(公告)号：US20160329289A1

公开(公告)日：2016-11-10

申请号：US14702984

申请日：2015-05-04

申请人： GLOBALFOUNDRIES INC.

发明人： Thomas J. Brunschwiler ,  Eric D. Perfecto ,  Jonas Zuercher

IPC分类号： H01L23/00 ,  B23K31/02 ,  B23K1/00

CPC分类号： H01L24/10 ,  B23K1/0016 ,  B23K1/0053 ,  B23K1/008 ,  B23K1/012 ,  B23K1/20 ,  B23K31/02 ,  B23K35/02 ,  B23K2101/42 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13687 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81909 ,  H01L2224/81911 ,  H01L2224/8192 ,  H01L2224/81986 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81948

摘要： A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

摘要翻译： 一种形成用于半导体器件的堆叠表面布置的方法包括：将第一表面与第二表面焊接在一起，所述焊料凸块包括基本上纯的第一金属; 将第二金属的纳米颗粒沉积到所述焊料凸块的表面上; 执行退火操作以在所述焊料凸块的表面上形成所述第二金属的膜; 以及执行回流或第二退火操作以将焊料凸块从基本上纯的第一金属转变为第一金属和第二金属的合金。

公开(公告)号：US09449913B2

公开(公告)日：2016-09-20

申请号：US13994668

申请日：2011-10-28

申请人： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

发明人： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/291 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

摘要翻译： 描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

公开(公告)号：US09406662B2

公开(公告)日：2016-08-02

申请号：US14763095

申请日：2014-03-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： François Marion ,  Alexis Bedoin ,  Frédéric Berger ,  Alain Gueugnot

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L27/146 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/1465 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13618 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13669 ,  H01L2224/16052 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2741 ,  H01L2224/27618 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/83191 ,  H01L2224/83859 ,  H01L2224/83862 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2224/83986 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2224/83 ,  H01L2924/01074 ,  H01L2224/27 ,  H01L2224/274 ,  H01L2224/276

摘要： A method of assembling a first and a second electronic components includes forming connection elements on an assembly surface of the first component and forming connection elements on an assembly surface of the second component. The method also includes depositing a liquid layer of electrically-insulating curable material on the assembly surface of the first and/or of the second component and arranging the first and second components on each other to place the connection elements of the second component in front of the connection elements of the first component. The method further includes applying a force along a predetermined direction and the first and/or the second components to create electric interconnects each formed of a connection element of the first component and of a connection element of the second component and curing the curable material.

摘要翻译： 组装第一和第二电子部件的方法包括在第一部件的组装表面上形成连接元件，并在第二部件的组装表面上形成连接元件。 该方法还包括将电绝缘的可固化材料的液体层沉积在第一和/或第二部件的组装表面上，并将第一和第二部件彼此排列以将第二部件的连接元件放置在 第一个组件的连接元素。 该方法还包括沿着预定方向施加力并且施加第一和/或第二部件以产生每个由第一部件的连接元件和第二部件的连接元件形成的电互连，并固化可固化材料。