公开(公告)号：US09685396B2

公开(公告)日：2017-06-20

申请号：US14865985

申请日：2015-09-25

申请人： NXP B.V.

发明人： Deorex David Avila Navaja

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/34 ,  H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/4951 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/13033 ,  H01L2924/13034 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor die arrangement comprising a first die including at least one semiconductor device; a second die including at least one semiconductor device; a lead frame associated with the first die and comprising one or more lead fingers, wherein the second die is mounted on one of the lead fingers and electrically connected to a further element by a bond wire.

公开(公告)号：US09682539B2

公开(公告)日：2017-06-20

申请号：US14417898

申请日：2012-07-30

申请人： Erich Thallner

发明人： Erich Thallner

IPC分类号： H01L21/00 ,  H01L21/20 ,  B32B37/00 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  B32B7/04 ,  B32B37/18 ,  H01L23/10 ,  H01L25/065 ,  H01L23/498 ,  H01L23/544

CPC分类号： B32B37/0076 ,  B32B7/045 ,  B32B37/18 ,  B32B2457/14 ,  H01L21/6835 ,  H01L23/10 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/131 ,  H01L2224/14145 ,  H01L2224/276 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/2902 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32052 ,  H01L2224/32055 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75253 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10155 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T428/24826 ,  Y10T428/24942 ,  H01L2224/83 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method for bonding a first substrate to a second substrate including the steps of: making contact of a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, as a result of which a common contact area is formed; and producing a bond interconnection between the first substrate and the second substrate outside the common contact area. The invention also relates to a corresponding device and a substrate composite of a first substrate and a second substrate, in which a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, forms a common contact area, outside the common contact area there being a bond interconnection between the first substrate and the second substrate.

公开(公告)号：US09679838B2

公开(公告)日：2017-06-13

申请号：US15165323

申请日：2016-05-26

申请人： Invensas Corporation

发明人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC分类号： H01L23/498 ,  H01L23/482 ,  H01L23/48 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  H01L23/31 ,  H01L25/10 ,  H01L25/16 ,  H01L23/13 ,  H01L23/50 ,  H01L23/52 ,  H01L27/108 ,  H01L23/00

CPC分类号： H01L23/49838 ,  G11C5/04 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06156 ,  H01L2224/06164 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

公开(公告)号：US09673161B2

公开(公告)日：2017-06-06

申请号：US15212970

申请日：2016-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Cha ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tsung-Hsien Chiang ,  Hao-Juin Liu ,  Yao-Chun Chuang ,  Chita Chuang

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L24/17 ,  H01L21/76897 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1301 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14152 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16505 ,  H01L2224/171 ,  H01L2224/17104 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841

摘要： The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

公开(公告)号：US09673158B2

公开(公告)日：2017-06-06

申请号：US14630265

申请日：2015-02-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Ding Wang ,  Hung-Jen Lin ,  Chien-Hsun Lee

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L24/11 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/16 ,  H01L24/18 ,  H01L24/81 ,  H01L2224/02379 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11515 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2224/64

摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

公开(公告)号：US09666563B2

公开(公告)日：2017-05-30

申请号：US14958226

申请日：2015-12-03

申请人： International Business Machines Corporation

发明人： Tien-Jen Cheng ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/488 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/488 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/038 ,  H01L2224/03825 ,  H01L2224/03829 ,  H01L2224/039 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/27464 ,  H01L2224/27831 ,  H01L2224/32145 ,  H01L2224/32146 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80895 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/1011 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2224/05155 ,  H01L2924/00012 ,  H01L2924/01046 ,  H01L2224/03616 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/05552

摘要： The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

公开(公告)号：US20170148710A1

公开(公告)日：2017-05-25

申请号：US15356598

申请日：2016-11-20

申请人： Semikron Elektronik GmbH & Co., KG

发明人： Frank STEIGLER ,  Stefan Schmitt ,  Harald Kobolla

IPC分类号： H01L23/495 ,  H02M7/00 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/1427 ,  H01L2924/19107 ,  H02M7/003 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： A power electronic switching device having plurality of potential surfaces. At least two different potentials are respectively assigned to at least one of the potential surfaces. A plurality of semiconductor components are arranged in an n×m matrix, oriented in the x-y-direction, on a first conductor track, formed by at least one potential surface of the first potential. The semiconductor components are connected in parallel with one another and form a current valve. In this case, the semiconductor components can be distributed among a plurality of potential surfaces of the first potential which form the first conductor track.

公开(公告)号：US09659890B2

公开(公告)日：2017-05-23

申请号：US14853006

申请日：2015-09-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/525

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US20170141017A1

公开(公告)日：2017-05-18

申请号：US15421515

申请日：2017-02-01

申请人： Semiconductor Components Industries, LLC

发明人： Roger M. Arbuthnot ,  Stephen St. Germain

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/67 ,  H01L24/73 ,  H01L24/83 ,  H01L24/89 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/37011 ,  H01L2224/37012 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207 ,  H01L2224/37099

摘要： In one embodiment, methods for making semiconductor devices are disclosed.

公开(公告)号：US09653669B2

公开(公告)日：2017-05-16

申请号：US15220294

申请日：2016-07-26

申请人： LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD. ,  LITE-ON TECHNOLOGY CORPORATION

发明人： Chih-Yuan Chen ,  Tien-Yu Lee

IPC分类号： H01L21/20 ,  H01L33/62 ,  H01L33/50 ,  H01L33/52 ,  H01L33/60 ,  H01L33/48

CPC分类号： H01L33/62 ,  H01L24/48 ,  H01L33/486 ,  H01L33/501 ,  H01L33/504 ,  H01L33/505 ,  H01L33/52 ,  H01L33/60 ,  H01L2224/05552 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2933/0041 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

摘要： An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet.