公开(公告)号：US20170025381A1

公开(公告)日：2017-01-26

申请号：US14806888

申请日：2015-07-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Cheng Tsai ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Yan-Chih Lu ,  Ju-Shi Chen

IPC分类号： H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L25/00 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L25/0657 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2224/80

摘要： An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

摘要翻译： 提供了使用基于铜合金的混合键的集成电路（IC）。 IC包括彼此垂直堆叠的一对半导体结构。 该对半导体结构包括布置在电介质层中的对应介电层和相应的金属特征。 金属特征包括具有铜和二次金属的铜合金。 IC还包括布置在半导体结构之间的界面处的混合键。 混合键包括将电介质层结合在一起的第一键和将金属特征粘合在一起的第二键。 第二结合包括布置在金属特征的铜颗粒之间并由二次金属填充的空隙。 还提供了使用基于铜合金的混合键将一对半导体结构结合在一起的方法。

公开(公告)号：US20170005234A1

公开(公告)日：2017-01-05

申请号：US15265487

申请日：2016-09-14

申请人： OSRAM Opto Semiconductors GmbH

发明人： Michael Fehrer ,  Alfred Lell ,  Martin Müller ,  Tilman Schlenker ,  Sönke Tautz ,  Uwe Strauß

IPC分类号： H01L33/44 ,  H01L33/62 ,  H01L31/18 ,  H01L31/02 ,  H01L31/0216 ,  H01L33/00 ,  H01L33/56 ,  H01L31/0203

CPC分类号： H01L33/44 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L31/02019 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/186 ,  H01L33/0095 ,  H01L33/56 ,  H01L33/62 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2933/0025 ,  H01L2933/005 ,  H01S5/02 ,  H01S5/028 ,  H01S5/20 ,  H01S2301/176 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An optoelectronic component includes at least one inorganic optoelectronically active semiconductor component having an active region that emits or receives light during operation, and a sealing material directly applied by atomic layer deposition, wherein the semiconductor component is applied on a carrier, the carrier includes electrical connection layers, the semiconductor component electrically connects to one of the electrical connection layers via an electrical contact element, and the sealing material completely covers in a hermetically impermeable manner and directly contacts all exposed surfaces including sidewall and bottom surfaces of the semiconductor component and the electrical contact element and all exposed surfaces of the carrier apart from an electrical connection region of the carrier.

摘要翻译： 光电子部件包括至少一个无机光电活性半导体部件，其具有在操作期间发射或接收光的有源区，以及通过原子层沉积直接施加的密封材料，其中半导体部件被施加在载体上，载体包括电连接 半导体部件经由电接触元件电连接到一个电连接层，并且密封材料完全以气密不渗透的方式覆盖，并且直接接触包括半导体部件的侧壁和底表面的所有暴露表面以及电接触 元件和载体的所有暴露表面与载体的电连接区域分开。

公开(公告)号：US09508630B2

公开(公告)日：2016-11-29

申请号：US14320686

申请日：2014-07-01

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Shinya Suzuki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  G02F1/1345 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/13 ,  H01L29/78

CPC分类号： H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

摘要： A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.

摘要翻译： 一种提高半导体芯片的凸块电极与安装基板的配线之间的耦合可靠性的技术，更具体地说，即使在布线位于突起电极下方的顶部布线层中时也能保证凸块电极的平坦度的技术，由此 提高凸起电极和形成在玻璃基板上的布线之间的耦合的可靠性。 在突起电极的非重叠区域下方的顶部布线层中形成由电力线或信号线构成的布线和虚设图案。 虚拟图案位于填充布线之间的空间以减少由布线引起的不规则和顶部布线层中的空间。 形成为覆盖顶部布线层的冲浪保护膜被CMP平坦化。

公开(公告)号：US09461224B2

公开(公告)日：2016-10-04

申请号：US14866060

申请日：2015-09-25

申请人： SHARP KABUSHIKI KAISHA

发明人： Masahiro Konishi ,  Masaki Kondo ,  Takaaki Horio ,  Takanobu Matsuo ,  Toshio Hata ,  Kiyohisa Ohta

IPC分类号： H01L33/00 ,  H01L33/62 ,  H01L23/00 ,  H01L33/60 ,  H01L33/56 ,  H01L33/50 ,  F21Y101/02 ,  H01L25/075 ,  H01L33/46 ,  F21K99/00

CPC分类号： H01L33/62 ,  F21K9/23 ,  F21Y2101/00 ,  F21Y2115/10 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/46 ,  H01L33/50 ,  H01L33/56 ,  H01L33/60 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2933/0066 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A light-emitting apparatus of the present invention has (i) a semiconductor device which emits light toward a higher position than a substrate and (ii) a plurality of external connection terminals, and includes: a light-reflecting layer, provided on the substrate, which reflects the light emitted by the semiconductor device; and a covering layer which covers at least the light-reflecting layer and which transmits the light reflected by the light-reflecting layer. Further, the semiconductor device is provided on the covering layer, and is electrically connected to the external connection terminals via connecting portions, and the semiconductor device and the connecting portions are sealed with a sealing resin so as to be covered. Therefore, the light-emitting apparatus has increased efficiency with which light is taken out, and can prevent a reflecting layer from being altered, deteriorating, and decreasing in reflectance.

公开(公告)号：US20160276315A1

公开(公告)日：2016-09-22

申请号：US15167904

申请日：2016-05-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Ming Chen ,  Cheng-Hsien Hsieh ,  Sung-Hui Huang ,  Kuo-Ching Hsu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L24/16 ,  B23K1/0016 ,  B23K2101/40 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/16145 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/81

摘要： A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

摘要翻译： 三维芯片堆叠包括结合到第二芯片的第一芯片以在它们之间形成电互连。 键合的互连包括覆盖第一芯片的第一衬底的第一导电柱，覆盖第二芯片的第二衬底的第二导电柱以及第一导电柱和第二导电柱之间的接合结构。 接头结构包括与第一导电柱相邻的第一IMC区域，与第二导电柱相邻的第二IMC区域以及在第一IMC区域和第二IMC区域之间的金属化层。

公开(公告)号：US20160240505A1

公开(公告)日：2016-08-18

申请号：US15024682

申请日：2014-11-11

申请人： NIPPON STEEL & SUMITOMO METAL CORPORATION ,  WASEDA UNIVERSITY

发明人： Kohei TATSUMI ,  Shinji ISHIKAWA ,  Norie MATSUBARA ,  Masamoto TANAKA

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  B22F7/08 ,  B22F2999/00 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/28 ,  B23K35/30 ,  B23K35/3033 ,  C22C5/06 ,  C22C5/08 ,  C22C19/00 ,  C22C21/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2741 ,  H01L2224/29083 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2949 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/83055 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8384 ,  H01L2224/85207 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00015 ,  B22F1/0018 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/0104 ,  H01L2924/01026 ,  H01L2924/01025 ,  H01L2924/01047 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/00012

摘要： The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.

摘要翻译： 本发明可以使用金属纳米粒子连接相同类型或不同类型的金属的接合结构，其中当一个表面金属为Al时，通过包含Ni纳米颗粒的接合层将部件接合，从而获得良好的接合强度。 此外，通过使用包含金属纳米颗粒的两个接合层（6,8）夹住金属箔（7）以形成接合层并通过该接合层接合相同类型或不同类型的表面金属（3-4） 由于具有两个表面金属的接合部件的热膨胀量的差异，可以减轻热应力。

公开(公告)号：US09391066B2

公开(公告)日：2016-07-12

申请号：US14712689

申请日：2015-05-14

申请人： Renesas Electronics Corporation

发明人： Shinya Suzuki ,  Kiichi Makuta

IPC分类号： H01L27/02 ,  H01L23/00 ,  H01L23/498 ,  G02F1/1345 ,  H01L23/532

CPC分类号： H01L24/17 ,  G02F1/13306 ,  G02F1/13452 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0292 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/9211 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

公开(公告)号：US09355980B2

公开(公告)日：2016-05-31

申请号：US14016966

申请日：2013-09-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Ming Chen ,  Cheng-Hsien Hsieh ,  Sung-Hui Huang ,  Kuo-Ching Hsu

IPC分类号： H01L23/00 ,  B23K1/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/16 ,  B23K1/0016 ,  B23K2101/40 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/16145 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/81

摘要： A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

摘要翻译： 三维芯片堆叠包括结合到第二芯片的第一芯片以在它们之间形成结合的互连。 键合的互连包括覆盖第一芯片的第一衬底的第一导电柱，覆盖第二芯片的第二衬底的第二导电柱以及第一导电柱和第二导电柱之间的接合结构。 接头结构包括与第一导电柱相邻的第一IMC区域，与第二导电柱相邻的第二IMC区域以及在第一IMC区域和第二IMC区域之间的金属化层。

公开(公告)号：US09337164B2

公开(公告)日：2016-05-10

申请号：US14525855

申请日：2014-10-28

申请人： Freescale Semiconductor, Inc.

发明人： Rama I. Hegde

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48

CPC分类号： H01L24/45 ,  H01L21/4821 ,  H01L21/4846 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45573 ,  H01L2224/45647 ,  H01L2224/45666 ,  H01L2224/45681 ,  H01L2224/45687 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2924/00012

摘要： A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

摘要翻译： 用于铜集成电路互连和其它导电结构的涂层阻碍并减少这种导电结构表面上的氧化物生长。 涂层包括沉积在结晶铜基底上的非晶态含铜层，例如用于引线框架和接合线。 可以在非晶态含铜层和铜基板之间插入附加非晶层，例如非晶氮化钽层和无定形氮化钛层。

公开(公告)号：US20160086911A1

公开(公告)日：2016-03-24

申请号：US14953390

申请日：2015-11-29

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Shinya Suzuki

IPC分类号： H01L23/00 ,  G02F1/1345

CPC分类号： H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

摘要： A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.