公开(公告)号：US20130127051A1

公开(公告)日：2013-05-23

申请号：US13745491

申请日：2013-01-18

申请人： MARVELL WORLD TRADE LTD.

发明人： Sehat Sutardja

IPC分类号： H01L23/498

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/92 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.

摘要翻译： 半导体封装包括具有第一表面的衬底，与第一表面相对的第二表面，以及形成在衬底的第一表面和衬底的第二表面之间的开口。 一个或多个接合线通过衬底的开口将包括在半导体封装中的半导体管芯的第一表面电耦合到衬底的第一表面。 第一电绝缘结构被设置为基本上填充半导体管芯的第一表面，衬底的第二表面与将半导体管芯电耦合到衬底的一个或多个互连凸块之间的区域。 第一电绝缘结构基本上封装一个或多个接合线并且基本上填充衬底的开口。

公开(公告)号：US08338925B2

公开(公告)日：2012-12-25

申请号：US12974744

申请日：2010-12-21

申请人： Joseph Fjelstad ,  Konstantine Karavakis

发明人： Joseph Fjelstad ,  Konstantine Karavakis

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/29

CPC分类号： H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/498 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85424 ,  H01L2924/00011 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004

摘要： A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

摘要翻译： 兼容的半导体芯片封装组件包括具有多个芯片触点的半导体芯片和具有顶表面，底表面和倾斜周边边缘的柔性层，由此柔性层的底表面覆盖在半导体芯片的表面上。 组件还包括连接到半导体芯片的芯片触点的多个导电迹线，迹线沿倾斜边缘延伸到柔性层的顶表面。 组件可以包括覆盖半导体芯片的导电端子，其中柔性层将导电端子支撑在半导体芯片上。 导电迹线具有与半导体芯片的触点电连接的第一端和与导电端子电连接的第二端。 导电端子可相对于半导体芯片移动。

公开(公告)号：US20120312428A1

公开(公告)日：2012-12-13

申请号：US13499977

申请日：2011-06-10

申请人： Michitaka Mikami

发明人： Michitaka Mikami

IPC分类号： C22C5/02

CPC分类号： C22C5/02 ,  B23K35/0227 ,  B23K35/0261 ,  B23K35/3013 ,  C22F1/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/05624 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01327 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2224/48 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/01006

摘要： To acquire the best combination of elongation and break strength on the Au alloy bonding wire. Adding 0.5-30 wt % of at least one element among Cu, Ag, Pd and Pt to high purity Au, a flat area about elongation ratio change appears between the range of 450-650° C. of heat-treatment temperature at wire drawing. Though the wire strength becomes decrease at this range of temperature, the strength is maintained at higher level against the heat treatment temperature of a standard elongation ratio of 4% of high purity Au alloy wire. Therefore, by the heat treatment of this flat range, Au alloy bonding wire, which has certain level of strength regardless of the temperature change, is acquired. Moreover, by selecting appropriate temperature range, different strength characteristics wires corresponding to the elongation ratio are acquired.

摘要翻译： 获得Au合金接合线上伸长率和断裂强度的最佳组合。 在Cu，Ag，Pd和Pt中添加0.5-30重量％的至少一种元素到高纯度Au，拉伸比变化的平坦区域出现在拉丝热处理温度的450-650℃的范围内 。 尽管在该温度范围内线材强度降低，但是相对于标准伸长率为4％的高纯度Au合金线材的热处理温度，强度保持在较高水平。 因此，通过该平坦范围的热处理，获得了具有一定水平的强度而不管温度变化的Au合金接合线。 此外，通过选择适当的温度范围，获得与伸长率对应的不同的强度特性线。

公开(公告)号：US20120306077A1

公开(公告)日：2012-12-06

申请号：US13530383

申请日：2012-06-22

申请人： Takekazu Tanaka ,  Kouhei Takahashi ,  Seiji Okabe

发明人： Takekazu Tanaka ,  Kouhei Takahashi ,  Seiji Okabe

IPC分类号： H01L23/498

CPC分类号： H01L24/05 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01203 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/00012 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2924/01006

摘要： A semiconductor device includes an electrode pad provided on a semiconductor chip, the electrode pad includes aluminum (Al) of between 50% wt. and 99.9% wt. and further includes copper (Cu), a coupling ball that primarily includes Cu, the coupling ball being coupled to the electrode pad so that a CuAl2 layer, a CuAl layer, a layer including one of Cu9Al4 and Cu3Al2, and the coupling ball are vertically stacked in this order on the electrode pad, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and a junction between the electrode pad and the coupling ball.

摘要翻译： 半导体器件包括设置在半导体芯片上的电极焊盘，所述电极焊盘包括铝（Al）的50重量％ 和99.9％wt。 并且还包括铜（Cu），主要包括Cu的耦合球，耦合球耦合到电极焊盘，使得CuAl 2层，CuAl层，包括Cu9Al4和Cu3Al2中的一个的层以及耦合球是垂直的 以及包含小于或等于1000ppm的卤素的封装树脂，至少覆盖电极焊盘的封装树脂和电极焊盘与联接球之间的连接点。

公开(公告)号：US08314484B2

公开(公告)日：2012-11-20

申请号：US12691175

申请日：2010-01-21

申请人： Ryoichi Kajiwara ,  Shigehisa Motowaki ,  Kazutoshi Ito ,  Toshiaki Ishii ,  Katsuo Arai ,  Takuya Nakajo ,  Hidemasa Kagii

发明人： Ryoichi Kajiwara ,  Shigehisa Motowaki ,  Kazutoshi Ito ,  Toshiaki Ishii ,  Katsuo Arai ,  Takuya Nakajo ,  Hidemasa Kagii

IPC分类号： H01L23/15

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/8392 ,  H01L2224/83951 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/05432 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2924/3512 ,  H01L2224/48744

摘要： In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

摘要翻译： 在半导体器件的结构中，Si芯片和金属引线框通过金属接合，通过具有三维网状结构的高导电性金属的多孔接合层，使用Ag作为接合材料，以及含有 在与聚合物树脂接触的半导体组件的表面上形成氧化锌或氧化铝。 以这种方式，通过与主要由Ag形成的多孔结构的接合层的接合，可以降低Si片的热应力负荷，并且可以提高接合层本身的疲劳寿命。 此外，由于通过锚固效应可以提高聚合物树脂对膜的粘附性，可以防止接合部发生裂纹，从而可以提供高可靠性的无铅半导体器件。

公开(公告)号：US20120289001A1

公开(公告)日：2012-11-15

申请号：US13560786

申请日：2012-07-27

申请人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L21/60

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 制造焊料顶部器件的方法包括将顶部金属层光刻地图案化成接触区域和接触增强区域; 然后使用用于增加的复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US20120241931A1

公开(公告)日：2012-09-27

申请号：US13069980

申请日：2011-03-23

申请人： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Jairus Legaspi Pisigan ,  Rachel Layda Abinan

发明人： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Jairus Legaspi Pisigan ,  Rachel Layda Abinan

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/85181 ,  H01L2224/85207 ,  H01L2224/85375 ,  H01L2224/85801 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; embedding a circuit end of an internal interconnect in the bonding interconnect; and connecting a lead end of the internal interconnect to the lead.

摘要翻译： 一种制造集成电路封装系统的方法包括：提供与所述管芯焊盘相邻的管芯焊盘和引线; 在芯片上安装具有接合焊盘的集成电路; 在所述接合焊盘上形成接合互连; 在接合互连中嵌入内部互连的电路端; 并将内部互连的引线端连接到引线。

公开(公告)号：US20120217660A1

公开(公告)日：2012-08-30

申请号：US13358840

申请日：2012-01-26

申请人： Motoaki TANI ,  Keishiro Okamoto

发明人： Motoaki TANI ,  Keishiro Okamoto

IPC分类号： H01L23/34 ,  H01L21/52

CPC分类号： H01L24/83 ,  H01L21/78 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/49822 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33183 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48666 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48766 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/1047 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13064 ,  H01L2924/142 ,  H01L2924/15153 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/00

摘要： A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

摘要翻译： 半导体装置包括：半导体器件，包括第一电极; 包括第二电极和凹部的基板; 以及散热粘合剂材料，用于将所述半导体器件设置在所述凹部中，以将所述第一电极布置成靠近所述第二电极，其中所述第一电极耦合到所述第二电极，并且所述散热粘合剂材料覆盖底表面， 半导体器件的侧表面的至少一部分。

公开(公告)号：US20120104613A1

公开(公告)日：2012-05-03

申请号：US13349155

申请日：2012-01-12

申请人： Tomohiro Uno ,  Keiichi Kimura ,  Shinichi Terashima ,  Takashi Yamada ,  Akihito Nishibayashi

发明人： Tomohiro Uno ,  Keiichi Kimura ,  Shinichi Terashima ,  Takashi Yamada ,  Akihito Nishibayashi

IPC分类号： H01L23/532

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/4312 ,  H01L2224/4321 ,  H01L2224/43825 ,  H01L2224/43847 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/456 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/45671 ,  H01L2224/45673 ,  H01L2224/4568 ,  H01L2224/45684 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/78251 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85048 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/859 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01105 ,  H01L2924/01204 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/15747 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/3025 ,  H01L2924/3861 ,  H01L2924/01001 ,  H01L2924/01203 ,  H01L2924/01034 ,  H01L2924/01081 ,  H01L2924/20645 ,  H01L2924/20652 ,  H01L2924/20653 ,  H01L2924/00014 ,  H01L2924/20108 ,  H01L2224/45657 ,  H01L2224/45666 ,  H01L2924/01008 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2076 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/20654 ,  H01L2924/00 ,  H01L2224/45124 ,  H01L2924/013 ,  H01L2924/20751 ,  H01L2924/2075 ,  H01L2924/00013 ,  H01L2924/01049

摘要： It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 μm in thickness.

摘要翻译： 本发明的目的是提供一种铜基接合线，其材料成本低，具有优异的球接合性，热循环试验或回流试验的可靠性以及储存寿命，使得能够使用的线材变薄 用于细间距连接。 接合线包括具有铜作为主要成分的芯材和设置在芯材上并且包含金属M和铜的外层，其中金属M与芯材料在组分和组成中的一种或两种中不同 。 外层的厚度为0.021〜0.12μm。

公开(公告)号：US20120100672A1

公开(公告)日：2012-04-26

申请号：US13342876

申请日：2012-01-03

申请人： Michael Brooks

发明人： Michael Brooks

IPC分类号： H01L21/58

CPC分类号： H01L24/49 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00012 ,  H01L2924/01004 ,  H01L2924/00013 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757

摘要： An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate having a plurality of bond pads; a first semiconductor device mounted on the package substrate, the first semiconductor device having a plurality of bond pads provided thereon; an interposer mounted on the first semiconductor device, the interposer having a first interposer bond pad and a second interposer bond pad, wherein the first and second interposer bond pads are electrically coupled; a second semiconductor device mounted on the interposer, the second semiconductor device having a plurality of bond pads provided thereon; a first bond wire connected to one of the plurality of bond pads on said first semiconductor and to the first interposer bond pad; and a second bond wire connected to the second interposer bond pad and to one of the plurality of bond pads on the semiconductor device.

摘要翻译： 改进的堆叠管芯封装包括提供封装的可制造性的插入件。 半导体封装包括具有多个接合焊盘的封装基板; 安装在所述封装基板上的第一半导体器件，所述第一半导体器件具有设置在其上的多个接合焊盘; 安装在所述第一半导体器件上的插入器，所述插入器具有第一插入器接合焊盘和第二插入器接合焊盘，其中所述第一和第二插入器接合焊盘电耦合; 安装在所述插入件上的第二半导体器件，所述第二半导体器件具有设置在其上的多个接合焊盘; 连接到所述第一半导体上的所述多个接合焊盘之一和所述第一插入器接合焊盘的第一接合线; 以及连接到第二插入器接合焊盘和半导体器件上的多个接合焊盘之一的第二接合线。