公开(公告)号：US20240332247A1

公开(公告)日：2024-10-03

申请号：US18613110

申请日：2024-03-22

申请人： NICHIA CORPORATION

发明人： Hiroaki KAGEYAMA ,  Yuka IMADA ,  Hiroki HANAOKA

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L25/075 ,  H01L33/40 ,  H01L33/62

CPC分类号： H01L24/80 ,  H01L22/22 ,  H01L24/05 ,  H01L24/08 ,  H01L24/95 ,  H01L25/0753 ,  H01L33/40 ,  H01L33/62 ,  H01L2224/05644 ,  H01L2224/08225 ,  H01L2224/80052 ,  H01L2224/80201 ,  H01L2224/80444 ,  H01L2224/95 ,  H01L2924/12041 ,  H01L2933/0066

摘要： A method of manufacturing a light emitting device includes preparing a plurality of first elements including first bonding parts and a wiring substrate including a plurality of second bonding parts. The method further includes placing the first elements on the wiring substrate by bonding the first bonding parts and the second bonding parts under first bonding conditions, and bonding the first bonding parts and the second bonding parts under second bonding conditions by placing a buffer sheet on the first elements and applying pressure on the first elements via the buffer sheet towards the wiring substrate. The bonding conducted under the second bonding conditions is performed multiple times.

公开(公告)号：US20230378012A1

公开(公告)日：2023-11-23

申请号：US17896840

申请日：2022-08-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Der-Chyang Yeh ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Min-Chien Hsiao ,  Chun-Chiang Kuo ,  Tsung-Shu Lin

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L23/3192 ,  H01L21/568 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/20 ,  H01L25/105 ,  H01L24/19 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80896 ,  H01L2224/211 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1041 ,  H01L2224/19

摘要： In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die; a gap-fill dielectric between a first sidewall of the first integrated circuit die and a second sidewall of the second integrated circuit die; a protective cap overlapping the gap-fill dielectric, the first sidewall of the first integrated circuit die, and the second sidewall of the second integrated circuit die; and an isolation layer around the protective cap, the isolation layer disposed on the first integrated circuit die, and the second integrated circuit die.

公开(公告)号：US09859246B2

公开(公告)日：2018-01-02

申请号：US14917318

申请日：2014-12-18

申请人： EV GROUP E. THALLNER GMBH

发明人： Andreas Fehkuhrer

IPC分类号： H01L21/00 ,  H01L23/00 ,  B32B37/00 ,  H01L21/18 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  B32B38/18

CPC分类号： H01L24/80 ,  B32B37/0046 ,  B32B38/1841 ,  B32B38/1858 ,  B32B2309/105 ,  B32B2457/14 ,  H01L21/187 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/08 ,  H01L24/74 ,  H01L24/75 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/0224 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/75251 ,  H01L2224/75272 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/80 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80047 ,  H01L2224/80051 ,  H01L2224/80093 ,  H01L2224/80099 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80209 ,  H01L2224/80213 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2221/68304

摘要： A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

公开(公告)号：US20170301646A1

公开(公告)日：2017-10-19

申请号：US15604454

申请日：2017-05-24

申请人： IMEC VZW

发明人： Soon-Wook Kim ,  Lan Peng ,  Patrick Verdonck ,  Robert Miller ,  Gerald Peter Beyer ,  Eric Beyne

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L21/02065 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03845 ,  H01L2224/03848 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/32501 ,  H01L2224/80048 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/83031 ,  H01L2224/83047 ,  H01L2224/83048 ,  H01L2224/83359 ,  H01L2924/00012 ,  H01L2924/0504 ,  H01L2924/00014 ,  H01L2924/20106 ,  H01L2924/2011

摘要： The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

公开(公告)号：US20170062393A1

公开(公告)日：2017-03-02

申请号：US15193323

申请日：2016-06-27

申请人： Samsung Display Co., Ltd.

发明人： Mugyeom Kim

IPC分类号： H01L25/075 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62 ,  H01L33/06

CPC分类号： H01L24/97 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/03002 ,  H01L2224/04 ,  H01L2224/80003 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80224 ,  H01L2224/80401 ,  H01L2224/80417 ,  H01L2224/80423 ,  H01L2224/80424 ,  H01L2224/80438 ,  H01L2224/80439 ,  H01L2224/80444 ,  H01L2224/80447 ,  H01L2224/80455 ,  H01L2224/80464 ,  H01L2224/80466 ,  H01L2224/80469 ,  H01L2224/80471 ,  H01L2224/80478 ,  H01L2224/8048 ,  H01L2224/80484 ,  H01L2224/81001 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81401 ,  H01L2224/81417 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81438 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81471 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81484 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2224/95085 ,  H01L2224/951 ,  H01L2224/95136 ,  H01L2224/95144 ,  H01L2224/97 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0106 ,  H01L2924/01003 ,  H01L2924/0102 ,  H01L2224/80 ,  H01L2224/81 ,  H01L2221/68304 ,  H01L21/78 ,  H01L2221/68381

摘要： A method of manufacturing a display device includes: immersing a mask including openings, in a solution; seating light-emitting diode chips respectively in the openings of the mask; arranging a first flexible substrate including first wirings thereon, below the mask, and aligning the first wirings to respectively correspond to the openings of the mask; removing from the solution, the first flexible substrate with the first wirings corresponding to the openings of the mask together with the mask with the light-emitting diode chips seated in the openings thereof; bonding the light-emitting diode chips and the first wirings to each other; providing a second flexible substrate including second wirings thereon, and aligning the second wirings to respectively correspond to the light-emitting diode chips; and bonding the light-emitting diode chips and the second wirings to each other, to form the display device.

摘要翻译： 制造显示装置的方法包括：将包括开口的掩模浸入溶液中; 将座位发光二极管芯片分别放置在掩模的开口中; 在所述掩模下面布置包括第一布线的第一柔性基板，并且将所述第一布线对准于所述掩模的开口; 从溶液中除去第一柔性基板，其中第一布线对应于掩模的开口与掩模一起，发光二极管芯片位于其开口中; 将发光二极管芯片和第一布线彼此接合; 提供第二柔性基板，其上包括第二布线，并且将所述第二布线对准分别对应于所述发光二极管芯片; 并且将发光二极管芯片和第二布线彼此接合，以形成显示装置。

公开(公告)号：US20160343682A1

公开(公告)日：2016-11-24

申请号：US15230125

申请日：2016-08-05

申请人： Kabushiki Kaisha Toshiba

发明人： Atsuko KAWASAKI

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08111 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

摘要： Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

摘要翻译： 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。

公开(公告)号：US09179586B2

公开(公告)日：2015-11-03

申请号：US13702173

申请日：2011-07-05

申请人： Jean Brun

发明人： Jean Brun

IPC分类号： H05K3/30 ,  H05K13/04 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H05K1/02 ,  H05K1/03

CPC分类号： H05K13/046 ,  H01L23/13 ,  H01L23/4985 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/08238 ,  H01L2224/1134 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/32238 ,  H01L2224/73204 ,  H01L2224/80006 ,  H01L2224/80007 ,  H01L2224/80201 ,  H01L2224/80903 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81903 ,  H01L2224/83005 ,  H01L2224/83007 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/90 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H05K1/0281 ,  H05K1/038 ,  H05K1/189 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/0108 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/05552

摘要： A substrate provided with an electrically conducting wire coated with an electrically insulating material is impregnated with a polymerizable material. A reception area for a chip is formed on a surface of the substrate by means of deformation. The housing area is stiffened using the polymerizable material. The chip is disposed in the reception area and an electrical connection area of the chip is connected electrically to the electrically conducting wire of the substrate.

摘要翻译： 设置有涂覆有电绝缘材料的导电线的基板用可聚合材料浸渍。 通过变形在基板的表面上形成用于芯片的接收区域。 使用可聚合材料使住房区域变硬。 芯片设置在接收区域中，并且芯片的电连接区域电连接到基板的导电线。

公开(公告)号：US20150048523A1

公开(公告)日：2015-02-19

申请号：US14397038

申请日：2013-04-24

申请人： Tadatomo SUGA ,  BONDTECH CO., LTD.

发明人： Tadatomo Suga ,  Akira Yamauchi

IPC分类号： H01L25/065 ,  B23K31/02 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  B23K37/04 ,  B23K37/00

CPC分类号： H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

摘要： [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

摘要翻译： [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US20150044786A1

公开(公告)日：2015-02-12

申请号：US13963741

申请日：2013-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xin-Hua Huang ,  Xiaomeng Chen ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L21/67

CPC分类号： H01L24/94 ,  H01L21/67092 ,  H01L21/681 ,  H01L24/08 ,  H01L24/74 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00015 ,  H01L2224/80121 ,  H01L2924/00

摘要： Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.

摘要翻译： 对准系统和晶片接合对准系统和方法被公开。 在一些实施例中，用于晶片接合系统的对准系统包括用于监测第一晶片和第二晶片的对准的装置，以及用于调整第二晶片的位置的装置。 对准系统包括用于将第一晶片和第二晶片的相对位置反馈到用于调整第一晶片和第二晶片的接合工艺之前和期间的第二晶片的位置的装置的装置。

公开(公告)号：US08941147B2

公开(公告)日：2015-01-27

申请号：US13660497

申请日：2012-10-25

申请人： International Business Machines Corporation

发明人： Cheng-Wei Cheng ,  Shu-Jen Han ,  Masaharu Kobayashi ,  Ko-Tao Lee ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC分类号： H01L29/66

CPC分类号： H01L24/89 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L29/78603 ,  H01L29/78681 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03914 ,  H01L2224/05617 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/08245 ,  H01L2224/80004 ,  H01L2224/80006 ,  H01L2224/80052 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80379 ,  H01L2224/80801 ,  H01L2224/8083 ,  H01L2224/80894 ,  H01L2224/9202 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2224/03 ,  H01L2924/00

摘要： A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

摘要翻译： 一种用于制造的器件和方法，包括提供包括第一衬底和形成在第一衬底上的第一金属层的第一衬底组件以及包括形成在第二衬底上的第二衬底和第二金属层的第二衬底组件。 使用冷焊工艺将第一金属层接合到第二金属层，其中第一衬底和第二衬底之一包括用于形成晶体管器件的半导体沟道层。