公开(公告)号：US20100237489A1

公开(公告)日：2010-09-23

申请号：US12405403

申请日：2009-03-17

Applicant: Christopher D. Manack ,  Steven A. Kummerl

Inventor： Christopher D. Manack ,  Steven A. Kummerl

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L29/0657 ,  B81C1/00333 ,  B81C2203/0136 ,  H01L23/053 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05011 ,  H01L2224/05015 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A cavity package (100) for micrometer-scale MEMS devices surrounding the cavity (210) with the MEMS device (220) with a rim (232) of solder-wettable metal, and then covering the cavity with a roof (240) of solder spanning from rim to rim. A solder body, placed over the cavity to rest on the rim, is reflowed; the surface tension of the liquid solder is reduced by the interfacial tension of the rim metal so that the liquid solder spreads over the rim surface and thereby stretches the liquid ball to a plate-like roof over the cavity. After solidifying the solder, the solder-to-metal seal renders the cavity package hermetic.

Abstract translation: 一种用于微米级MEMS器件的空腔封装（100），所述腔体封装（100）围绕所述腔体（210），所述MEMS器件（220）具有焊料可润湿金属的边缘（232），然后用焊料顶部（240）覆盖所述腔体 从边缘到边缘。 放置在空腔上以放置在边缘上的焊料体被回流; 液体焊料的表面张力由于边缘金属的界面张力而降低，使得液体焊料在边缘表面上扩散，从而将液体球拉伸到空腔上的板状屋顶。 在焊接焊料固化之后，焊料对金属密封件使腔体封装成气密。

公开(公告)号：US06414390B2

公开(公告)日：2002-07-02

申请号：US09729959

申请日：2000-12-06

Applicant: Kazuhiko Nozawa

Inventor： Kazuhiko Nozawa

IPC: H01L2144

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/03436 ,  H01L2224/036 ,  H01L2224/0383 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal flyer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).

Abstract translation: 一种半导体器件及其制造方法，电路板和电子仪器使得在没有基板材料选择或连接后的附加步骤的情况下，可以确保连接可靠性，同时可直接连接到基板，还允许电子仪器 使其更加紧凑轻巧。 半导体器件包括具有电极（104）的半导体芯片（100），连接到电极（104）的互连层（120），设置在互连层（120）上的导电层（122），避免了电极 （104），具有比导电层（122）上设置并且比导电层（122）更容易变形的导电层（122）的外围轮廓的尺寸的底层金属飞翼（124），凸块（200） ）设置在下层金属层（124）上，树脂层（126）设置在导电层（122）的周围。

公开(公告)号：US20190244920A1

公开(公告)日：2019-08-08

申请号：US16384136

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Hsiung Lu ,  Hsuan-Ting Kuo ,  Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/525 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/04953 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

公开(公告)号：US09947632B2

公开(公告)日：2018-04-17

申请号：US15336774

申请日：2016-10-27

Applicant: Nexperia B.V.

Inventor： Chi Ho Leung ,  Pompeo V Umali ,  Shun Tik Yeung ,  Wai (Kan Wae) Lam

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/03013 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/013

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

公开(公告)号：US09922960B2

公开(公告)日：2018-03-20

申请号：US15196170

申请日：2016-06-29

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sumihiro Ichikawa

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83895 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00015 ,  H01L2924/14 ,  H05K3/328 ,  H05K3/368 ,  H05K3/4007 ,  H05K2203/167 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2224/81121 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/034 ,  H01L2224/113 ,  H01L2224/81203 ,  H01L2224/81201 ,  H01L2924/00

Abstract: A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal; and a second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the second substrate being provided on the first substrate, the first metal terminal and the third metal terminal being directly bonded with each other, and the second metal terminal and the fourth metal terminal being bonded via a connection portion.

公开(公告)号：US20170221843A1

公开(公告)日：2017-08-03

申请号：US15011122

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuei-Sung Chang ,  Nien-Tsung Tsai

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03618 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05686 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48228 ,  H01L2224/49109 ,  H01L2224/49173 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05341 ,  H01L2924/0535 ,  H01L2924/05432 ,  H01L2924/14 ,  H01L2924/206 ,  H01L2224/05599 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/053 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.

公开(公告)号：US20170098628A1

公开(公告)日：2017-04-06

申请号：US15212125

申请日：2016-07-15

Applicant: MediaTek Inc.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03011 ,  H01L2224/03502 ,  H01L2224/036 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06136 ,  H01L2224/06146 ,  H01L2224/06156 ,  H01L2224/06166 ,  H01L2224/10126 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/17136 ,  H01L2224/17146 ,  H01L2224/17156 ,  H01L2224/17166 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/214 ,  H01L2924/00

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body.

公开(公告)号：US20160307859A1

公开(公告)日：2016-10-20

申请号：US15193117

申请日：2016-06-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract translation: 本发明提供一种半导体器件，其包括衬底，电介质层，虚拟焊盘，焊盘，再分配层和金属互连。 衬底包括非器件区域和器件区域。 介电层位于非器件区域和器件区域上。 虚拟焊盘位于非器件区的介质层上。 金属互连在非器件区的介质层中并连接到虚拟焊盘。 焊盘位于器件区域的介电层上。 缓冲层位于接合焊盘和电介质层之间。 缓冲层包括金属，金属氮化物或其组合。 再分布层在电介质层上并连接虚拟焊盘和焊盘。

公开(公告)号：US09472483B2

公开(公告)日：2016-10-18

申请号：US14802341

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  Sebastian T. Ventrone

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/48 ,  H01L23/373 ,  H01L21/768 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/367 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/922 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract translation: 公开了一种由半导体材料制造的芯片，其可以包括位于从芯片背面的第一深度以下的有源器件，以及将热量从有源器件移除到芯片背面的结构。 该结构可以包括导热部分通孔（TCPV），其可以包括从芯片背侧朝向有源器件的深度的凹陷小于第一深度。 每个TCPV可以包括沉积在凹槽内并沉积在芯片背面的阻挡层。 每个TCPV还可以包括沉积在阻挡层上的导热层。 该结构还可以包括电连接到有源器件的穿硅通孔（TSV），其从芯片的背面延伸到有源器件侧，以将热量从有源器件导电移除到芯片的背面。

公开(公告)号：US20160284588A1

公开(公告)日：2016-09-29

申请号：US15174366

申请日：2016-06-06

Applicant: ROHM CO., LTD.

Inventor： Kenichi YOSHIMOCHI

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/02 ,  H01L29/866 ,  H01L21/763 ,  H01L27/06 ,  H01L27/118 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76237 ,  H01L21/76205 ,  H01L21/763 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/11896 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66106 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4911 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.