公开(公告)号：US09679859B2

公开(公告)日：2017-06-13

申请号：US14991560

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L29/40 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/013 ,  H01L2924/13091 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.

公开(公告)号：US09679858B2

公开(公告)日：2017-06-13

申请号：US15231820

申请日：2016-08-09

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki Sekikawa

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05664 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00013

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

公开(公告)号：US09673161B2

公开(公告)日：2017-06-06

申请号：US15212970

申请日：2016-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Hong Cha ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tsung-Hsien Chiang ,  Hao-Juin Liu ,  Yao-Chun Chuang ,  Chita Chuang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L21/76897 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1301 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14152 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16505 ,  H01L2224/171 ,  H01L2224/17104 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

公开(公告)号：US20170154857A1

公开(公告)日：2017-06-01

申请号：US15430582

申请日：2017-02-13

Applicant: Infineon Technologies AG

Inventor： Srinivasa Reddy Yeduru ,  Karl Heinz Gasser ,  Stefan Woehlert ,  Karl Mayer ,  Francisco Javier Santos Rodriguez

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L21/288 ,  H01L21/4814 ,  H01L21/6835 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/04026 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/27002 ,  H01L2224/27005 ,  H01L2224/2732 ,  H01L2224/2747 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29021 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29393 ,  H01L2224/32245 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05124 ,  H01L2224/05187 ,  H01L2924/0665 ,  H01L2924/01006 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/07802

Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

公开(公告)号：US09666540B2

公开(公告)日：2017-05-30

申请号：US14973946

申请日：2015-12-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Frederick R. Dahilig ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Dioscoro A. Merilo

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/36 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/433 ,  H01L23/34 ,  H01L21/48 ,  H01L21/78 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

公开(公告)号：US20170148754A1

公开(公告)日：2017-05-25

申请号：US15421737

申请日：2017-02-01

Applicant: GlobalFoundries Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US09640519B2

公开(公告)日：2017-05-02

申请号：US14737072

申请日：2015-06-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L29/06 ,  H01L23/498

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20170117245A1

公开(公告)日：2017-04-27

申请号：US15351184

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

公开(公告)号：US09627334B2

公开(公告)日：2017-04-18

申请号：US15278072

申请日：2016-09-28

Applicant: Texas Instruments Incorporated

Inventor： Manoj K. Jain

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

公开(公告)号：US09627290B2

公开(公告)日：2017-04-18

申请号：US13313867

申请日：2011-12-07

Applicant: Hsien-Wei Chen

Inventor： Hsien-Wei Chen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L23/3192 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13541 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/206 ,  H01L2224/05552

Abstract: Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.